Autonomous Creation of Analog Integrated Circuits based on Self-Learning of Design Expertise

Project Information

AnalogCreate

Grant agreement ID: 101019982

DOI

10.3030/101019982

EC signature date 29 June 2021

Start date 1 September 2021

End date 31 August 2027

Funded under

• EXCELLENT SCIENCE - European Research Council (ERC)

Total cost

€ 2 500 000,00

EU contribution

€ 2 500 000,00

Coordinated by

KATHOLIEKE UNIVERSITEIT LEUVEN
Belgium

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Links to deliverables and publications from FP7 projects, as well as links to some specific result types such as dataset and software, are dynamically retrieved from OpenAIRE .

Publications

Peer reviewed articles (5)

<i>SunPar</i> : An Analytical Design Space Exploration Framework Modeling Performance Uncertainty in Sparse AI Accelerators

Author(s): Jiacong Sun, Man Shi, Mahesh Subedar, Georges Gielen, Marian Verhelst
Published in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Issue 45, 2026, Page(s) 2222-2235, ISSN 0278-0070
Publisher: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tcad.2025.3613662

A Generalized Constraint Learning and Transfer Methodology with Net-First Graph Neural Network and Selective Topological Search for Hierarchical Analog / Mixed-Signal Circuit Layout Synthesis

Author(s): Kaichang Chen, Georges Gielen
Published in: ACM Transactions on Design Automation of Electronic Systems, Issue 31, 2026, Page(s) 1-32, ISSN 1084-4309
Publisher: Association for Computing Machinary, Inc.
DOI: 10.1145/3722556

Boosting Latent Defect Coverage in Automotive Mixed-Signal ICs using SVM Classifiers

Author(s): Nektar Xama; Jhon Gomez Caicedo; Georges Gielen
Published in: IEEE Transactions on Computer-Aided Design of Integrated Circuits And Systems, Issue 2023, 2023, ISSN 0278-0070
Publisher: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tcad.2023.3244892

AnaCraft: Duel-Play Probabilistic-Model-Based Reinforcement Learning for Sample-Efficient PVT-Robust Analog Circuit Sizing Optimization

Author(s): Mohsen Ahmadzadeh, Jan Lappas, Norbert Wehn, Georges Gielen
Published in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Issue 45, 2026, Page(s) 901-914, ISSN 0278-0070
Publisher: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tcad.2025.3582175

A Brief 20-Year History and Future Perspectives on Sizing and Layout Synthesis of Analog/RF ICs

Author(s): Georges G. E. Gielen
Published in: IEEE Design &amp; Test, Issue 42, 2025, Page(s) 63-74, ISSN 2168-2356
Publisher: IEEE Computer Society
DOI: 10.1109/mdat.2025.3603144

Other (4)

Analog synthesis 3.0: AI/ML to boost automated design and test ofanalog/mixed-signal ICs

Author(s): Georges Gielen
Published in: keynote presentation ASP-DAC 2023 conference, Issue 2023, 2023
Publisher: IEEE

AI in the edge; the edge of AI

Author(s): Georges Gielen
Published in: keynote presentation Design, Automation & Test in Europe (DATE) conference, Issue 2022, 2022
Publisher: IEEE CEDA

Machine-learning-based synthesis of analog integrated circuits exploiting the self-learning of design expertise

Author(s): Georges Gielen
Published in: invited presentation MPSoC'22 conference, Issue 2022, 2022
Publisher: EDAA/IEEE

DeepDesignAMS: Will Tomorrow’s Analog Integrated Circuits be Generated by AI?

Author(s): Georges Gielen
Published in: keynote presentation 2025 International Symposium of EDA (ISEDA), Issue 2025, 2025
Publisher: IEEE

Conference proceedings (7)

Using Probabilistic Model Rollouts to Boost the Sample Efficiency of Reinforcement Learning for Automated Analog Circuit Sizing

Author(s): Mohsen Ahmadzadeh, Georges G. E. Gielen
Published in: Proceedings of the 61st ACM/IEEE Design Automation Conference, Issue 2024, 2025, Page(s) 1-6
Publisher: ACM
DOI: 10.1145/3649329.3657335

Self-Learning and Transfer Across Topologies of Constraints for Analog / Mixed-Signal Circuit Layout Synthesis

Author(s): Kaichang Chen, Georges G.E. Gielen
Published in: 2024 Design, Automation &amp;amp; Test in Europe Conference &amp;amp; Exhibition (DATE), Issue 2024, 2024, Page(s) 1-6
Publisher: IEEE
DOI: 10.23919/date58400.2024.10546850

Graph-Guided Transfer Learning to Boost the Efficiency of System-Level Optimization of Analog/Mixed-Signal Circuits

Author(s): Jiaqi Wang, Georges G.E. Gielen
Published in: 2025 62nd ACM/IEEE Design Automation Conference (DAC), Issue 2025, 2025, Page(s) 1-7
Publisher: IEEE
DOI: 10.1109/dac63849.2025.11132596

Recent Trends and Perspectives on Defect-Oriented Testing

Author(s): P. Bernardi; R. Cantoro; A. Coyette; W. Dobbeleare; M. Fieback; A. Floridia; Georges Gielen; J. Gomez; M. Grosso; A. Guerriero; I. Guglielminetti; S. Hamdioui; G. Insinga; N. Mautone; N. Mirabella; S. Sartoni; M. Sonza Reorda; R. Ullmann; R. Vanhooren; Nektar Xama; L. Wu
Published in: proceedings 2022 IEEE 28TH INTERNATIONAL SYMPOSIUM ON ON-LINE TESTING AND ROBUST SYSTEM DESIGN (IOLTS 2022), Issue 2022, 2022
Publisher: IEEE
DOI: 10.1109/iolts56730.2022.9897647

Hybrid AI-Optimization Method for Latent Defect Detection Through Test Transistor Insertion in Analog Circuits

Author(s): Sankhya Bhattacharya, Georges Gielen
Published in: 2025 21st International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuits Design (SMACD), Issue 2025, 2025, Page(s) 1-4
Publisher: IEEE
DOI: 10.1109/smacd65553.2025.11092178

Analog synthesis 3.0: AI/ML to synthesize and test analog ICs: hope or hype ?

Author(s): Georges Gielen
Published in: proceedings ACM/IEEE Workshop on Machine Learning for CAD (MLCAD), Issue 2024, 2024
Publisher: ACM/IEEE
DOI: 10.1109/mlcad58807.2023.10299830

(Invited Paper) AnaFlow: Agentic LLM-based Workflow for Reasoning-Driven Explainable and Sample-Efficient Analog Circuit Sizing

Author(s): Mohsen Ahmadzadeh, Kaichang Chen, Georges Gielen
Published in: 2025 IEEE/ACM International Conference On Computer Aided Design (ICCAD), Issue 2025, 2025, Page(s) 1-7
Publisher: IEEE
DOI: 10.1109/iccad66269.2025.11240818