Autonomous Creation of Analog Integrated Circuits based on Self-Learning of Design Expertise

Project Information

AnalogCreate

Grant agreement ID: 101019982

DOI

10.3030/101019982

EC signature date 29 June 2021

Start date 1 September 2021

End date 31 August 2027

Funded under

• EXCELLENT SCIENCE - European Research Council (ERC)

Total cost

€ 2 500 000,00

EU contribution

€ 2 500 000,00

Coordinated by

KATHOLIEKE UNIVERSITEIT LEUVEN
Belgium

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Links to deliverables and publications from FP7 projects, as well as links to some specific result types such as dataset and software, are dynamically retrieved from OpenAIRE .

Publications

Conference proceedings (5)

Analog synthesis 3.0: AI/ML to boost automated design and test ofanalog/mixed-signal ICs

Author(s): Georges Gielen
Published in: proceedings ASP-DAC, Issue 2023, 2023
Publisher: IEEE

Using probabilistic model rollouts to boost the sample efficiency of reinforcement learning for automated analog circuit sizing

Author(s): Mohsen Ahmadzadeh; Georges Gielen
Published in: proceedings Design Automation Conference (DAC), Issue 2024, 2024
Publisher: ACM/IEEE

Self-learning and transfer across topologies of constraints for analog/mixed-signal circuit layout synthesis

Author(s): Kaichang Chen; Georges Gielen
Published in: proceedings Design, Automation & Test in Europe (DATE) conference, Issue 2024, 2024
Publisher: EDAA/IEEE/ACM
DOI: 10.23919/DATE58400.2024.10546850

Recent Trends and Perspectives on Defect-Oriented Testing

Author(s): P. Bernardi; R. Cantoro; A. Coyette; W. Dobbeleare; M. Fieback; A. Floridia; Georges Gielen; J. Gomez; M. Grosso; A. Guerriero; I. Guglielminetti; S. Hamdioui; G. Insinga; N. Mautone; N. Mirabella; S. Sartoni; M. Sonza Reorda; R. Ullmann; R. Vanhooren; Nektar Xama; L. Wu
Published in: proceedings 2022 IEEE 28TH INTERNATIONAL SYMPOSIUM ON ON-LINE TESTING AND ROBUST SYSTEM DESIGN (IOLTS 2022), Issue 2022, 2022
Publisher: IEEE
DOI: 10.1109/iolts56730.2022.9897647

Analog synthesis 3.0: AI/ML to synthesize and test analog ICs: hope or hype ?

Author(s): Georges Gielen
Published in: proceedings ACM/IEEE Workshop on Machine Learning for CAD (MLCAD), Issue 2024, 2024
Publisher: ACM/IEEE
DOI: 10.1109/mlcad58807.2023.10299830

Peer reviewed articles (1)

Boosting Latent Defect Coverage in Automotive Mixed-Signal ICs using SVM Classifiers

Author(s): Nektar Xama; Jhon Gomez Caicedo; Georges Gielen
Published in: IEEE Transactions on Computer-Aided Design of Integrated Circuits And Systems, Issue 2023, 2023, ISSN 0278-0070
Publisher: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tcad.2023.3244892

Other (2)

AI in the edge; the edge of AI

Author(s): Georges Gielen
Published in: keynote presentation Design, Automation & Test in Europe (DATE) conference, Issue 2022, 2022
Publisher: IEEE CEDA

Machine-learning-based synthesis of analog integrated circuits exploiting the self-learning of design expertise

Author(s): Georges Gielen
Published in: invited presentation MPSoC'22 conference, Issue 2022, 2022
Publisher: EDAA/IEEE