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Autonomous Creation of Analog Integrated Circuits based on Self-Learning of Design Expertise

Project description

Machine learning could accelerate the design of sophisticated analogue ci

The era of smart-everything has led to a surge in the need for advanced semiconductor technologies and intelligent data processing. Despite advances in the field, analogue circuit design lags behind its digital counterpart: analogue circuits are still produced in the laboratory, which results in error-prone cycles and high development costs. The EU-funded AnalogCreate project will tap into the potential of machine learning to speed up the design of advanced integrated circuits for promising information and communication applications. Project activities will enable for the first time the autonomous creation of affordable analogue circuits from specifications to fully verified layout – all without being amenable to human feedback.

Objective

Progress in semiconductor technology and in intelligent data processing are converging today, opening the door to countless smart ICT applications through the Cloud and Internet of Everything, to the peoples benefit in years to come. Applications that interact with the physical world (e.g. environmental sensing, healthcare, autonomous vehicles, etc.), also need analog integrated circuits in the cyber-physical or edge layer. But while digital circuits are largely synthesized automatically through software, the analog circuits are mainly still handcrafted in industry with low design productivity. This results in long and error-prone design cycles, and the high development costs jeopardize many potential new ICT applications from ever being realized (e.g. solutions for rare diseases). It becomes even more problematic when moving to advanced technologies below 16 nm CMOS, that come with way more design and layout rules to be dealt with. The showstopper for state-of-the-art analog synthesis tools is that they require design heuristics and constraints to be entered explicitly by designers in order to handle the humongous solution space and to steer the circuit and layout optimizations towards acceptable solutions. The proposed disruptively new approach is to use the self-learning capabilities of advanced machine learning algorithms to self-learn and then exploit the design expertise and constraints from the many available successfully completed designs. Also a true circuit topology synthesis approach will be developed to create a proper (possibly novel) schematic from the target specifications, as well as an innovative formal analog design verification approach based on Quick Error Detection. These innovations will enable for the first time ever to truly autonomously create analog circuits from specifications to fully verified layout without direct input from any designer in the loop, and therefore enable the affordable implementation of many promising ICT applications.

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Topic(s)

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Funding Scheme

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ERC-ADG - Advanced Grant

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Call for proposal

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(opens in new window) ERC-2020-ADG

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Host institution

KATHOLIEKE UNIVERSITEIT LEUVEN
Net EU contribution

Net EU financial contribution. The sum of money that the participant receives, deducted by the EU contribution to its linked third party. It considers the distribution of the EU financial contribution between direct beneficiaries of the project and other types of participants, like third-party participants.

€ 2 500 000,00
Address
OUDE MARKT 13
3000 Leuven
Belgium

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Region
Vlaams Gewest Prov. Vlaams-Brabant Arr. Leuven
Activity type
Higher or Secondary Education Establishments
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Total cost

The total costs incurred by this organisation to participate in the project, including direct and indirect costs. This amount is a subset of the overall project budget.

€ 2 500 000,00

Beneficiaries (1)

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