Seamless design of smart edge processors

Información del proyecto

CONVOLVE

Identificador del acuerdo de subvención: 101070374

DOI

10.3030/101070374

Fecha de la firma de la CE 23 Junio 2022

Fecha de inicio 1 Noviembre 2022

Fecha de finalización 30 Abril 2026

Financiado con arreglo a

• Digital, Industry and Space

Coste total

€ 8 418 127,50

Aportación de la UE

€ 8 416 876,50

Coordinado por

TECHNISCHE UNIVERSITEIT EINDHOVEN
Netherlands

CORDIS proporciona enlaces a los documentos públicos y las publicaciones de los proyectos de los programas marco HORIZONTE.

Los enlaces a los documentos y las publicaciones de los proyectos del Séptimo Programa Marco, así como los enlaces a algunos tipos de resultados específicos, como conjuntos de datos y «software», se obtienen dinámicamente de OpenAIRE .

Resultado final

Documents, reports (17)

Technical specification for neural accelerator hardware

Set of technical requirements for hardware accelerators for neural networks (to WP2)

Description SoC architecture, and the rapid design & prototyping environment

Report in detail the developed SoC architecture, and the first generation of the rapid design & prototyping environment useable by other partners.

Requirements, Threats, and Vulnerabilities Analysis

Description of the use cases security requirements, potential threats, and identified vulnerabilities

Intermediate Neural network resiliency analysis and AxC optimizations

Intermediate report of the NN resiliency analysis for AxC framework

Modular architecture template definition

Definition of high level SoC architecture and interfaces for accelerators, to be aligned with WP2/3.

Update of requirements and use cases

Update of D1.1 after the point demos are ready

Compiler prototype

Report and first prototype of our compiler and DSL framework, implementing constraints and opportunities in the compiler middle end. This deliverable is extended to incorporate topology-aware asymmetric CGRA arithmetic mappings;

Initial requirements and use cases

Description of the use cases, their first set of requirements and their technical specification. These are originating from all use cases on all aspects of the CONVOLVE objectives. An initial relationship between requirements and objectives to use-cases is provided.

Report on the roadmap

Definition of energy-efficient, reconfigurable, and self-healing accelerators.

Initial communication plan and reports

Initial definition of the communication plan and reporting of the communication activities carried out.

Initial Dissemination plan and report

Initial report on definition of the dissemination plan and reporting of the dissemination activities carried out

Intermediate report on the design of the targeted accelerator blocks

Definition of the micro-architecture of the targeted accelerators and design progress of the targeted accelerators.

Roadmap document for neural networks

Roadmap document for low power, high performance neural networks.

Description of the gen1 performance analysis framework and DSE framework

Report in detail the first generation of the developed performance analysis framework and DSE framework for heterogeneous ML platforms useable by other partners.

Constraints and opportunities definition

Integration design document on (security) constraints and (optimization) opportunities and compiler interface design, including interfaces with other WPs and open-source infrastructure (LLVM, MLIR).

Initial Memory management and allocation for ULP accelerators

Initial report and code of the MM customized to the CONVOLVE SoC architecture

Intermediate report on the accelerator simulator

Reporting the developed performance models and provides the progress of the simulator design to utilize the models

Websites, patent fillings, videos etc. (1)

Project identity set and website

Definition of project's identity set and website launch

Data Management Plan (1)

Data Management Plan

Data management plan based on FAIR principles

Publicaciones

Conference proceedings (32)

Late Breaking Results: Language-level QoR modeling for High-Level Synthesis

Autores: Dimosthenis Masouros, Aggelos Ferikoglou, Georgios Zervakis, Sotirios Xydis, Dimitrios Soudris
Publicado en: Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
Editor: ACM
DOI: 10.1145/3649329.3663500

SECOMP: Formally Secure Compilation of Compartmentalized C Programs

Autores: Jérémy Thibault, Roberto Blanco, Dongjae Lee, Sven Argo, Arthur Azevedo de Amorim, Aïna Linn Georges, Cătălin Hriţcu, Andrew Tolmach
Publicado en: Proceedings of the 2024 on ACM SIGSAC Conference on Computer and Communications Security, 2025
Editor: ACM
DOI: 10.1145/3658644.3670288

CMDS: Cross-layer Dataflow Optimization for DNN Accelerators Exploiting Multi-bank Memories

Autores: Man Shi; Steven Colleman MICAS-ESAT, KU Leuven ; Charlotte VanDeMieroop; Antony Joseph; Maurice Meijer; Wim Dehaene; Marian Verhelst
Publicado en: 2023 24th International Symposium on Quality Electronic Design (ISQED), 2023, ISSN 1948-3295
Editor: Institute of Electrical and Electronics Engineers
DOI: 10.1109/ISQED57927.2023.10129330

An Empirical Evaluation of Sliding Windows on Siren Detection Task using Spiking Neural Networks

Autores: Shreya Kshirasagar; Andre Guntoro; Christian Mayr
Publicado en: 6th International Conference on Advances in Signal Processing and Artificial Intelligence (ASPAI' 2024), 2024, ISSN 2938-5350
Editor: International Frequency Sensor Association
DOI: 10.13140/RG.2.2.23368.53763

ACCO: Automated Causal CNN Scheduling Optimizer for Real-Time Edge Accelerators

Autores: Jun Yin, Linyan Mei, Andre Guntoro, Marian Verhelst
Publicado en: """2023 IEEE 41st International Conference on Computer Design (ICCD) """, 2023, ISSN 2576-6996
Editor: ACM/IEEE
DOI: 10.1109/ICCD58817.2023.00065

HTVM: Efficient Neural Network Deployment On Heterogeneous TinyML Platforms

Autores: Josse Van Delm, Maarten Vandersteegen, Alessio Burrello, Giuseppe Maria Sarda, Francesco Conti, Daniele Jahier Pagliari, Luca Benini, Marian Verhelst
Publicado en: 2023 60th ACM/IEEE Design Automation Conference (DAC), 2024
Editor: IEEE
DOI: 10.1109/DAC56929.2023.10247664

ESAM: Energy-efficient SNN Architecture using 3nm FinFET Multiport SRAM-based CIM with Online Learning

Autores: Lucas Huijbregts, Liu Hsiao-Hsuan, Paul Detterer, Said Hamdioui, Amirreza Yousefzadeh, Rajendra Bishnoi
Publicado en: 2024
Editor: Proceedings of the 61st ACM/IEEE Design Automation Conference
DOI: 10.48550/arXiv.2410.09130

A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions

Autores: Alexandre Lopoukhine, Federico Ficarelli, Christos Vasiladiotis, Anton Lydike, Josse Van Delm, Alban Dutilleul, Luca Benini, Marian Verhelst, Tobias Grosser
Publicado en: Proceedings of the 23rd ACM/IEEE International Symposium on Code Generation and Optimization, 2025
Editor: ACM
DOI: 10.1145/3696443.3708952

Auditory Anomaly Detection using Recurrent Spiking Neural Networks

Autores: Shreya Kshirasagar; Benjamin Cramer; Andre Guntoro; Christian Mayr
Publicado en: IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2024, ISSN 2834-9857
Editor: IEEE
DOI: 10.1109/AICAS59952.2024.10595878

Dependability of Future Edge-AI Processors: Pandora’s Box

Autores: Manil Dev Gomony, Anteneh Gebregiorgis, Moritz Fieback, Marc Geilen, Sander Stuijk, Jan Richter-Brockmann, Rajendra Bishnoi, Sven Argo, Lara Arche Andradas, Tim Güneysu, Mottaqiallah Taouil, Henk Corporaal, Said Hamdioui
Publicado en: 2023 IEEE European Test Symposium (ETS), 2023, ISSN 1558-1780
Editor: Institute of Electrical and Electronics Engineers
DOI: 10.1109/ETS56758.2023.10174180

Optimizing Layer-Fused Scheduling of Transformer Networks on Multi-accelerator Platforms

Autores: Steven Colleman, Arne Symons, Victor J.B. Jung, Marian Verhelst
Publicado en: 2024 25th International Symposium on Quality Electronic Design (ISQED), 2024, ISSN 1948-3295
Editor: Institute of Electrical and Electronics Engineers
DOI: 10.1109/ISQED60706.2024.10528689

Verifying Peephole Rewriting In SSA Compiler IRs

Autores: Siddharth Bhat, Alex Keizer, Chris Hughes, Andres Goens and Tobias Grosser
Publicado en: 2024
Editor: Open Access
DOI: 10.48550/arXiv.2407.03685

Decoupled Access-Execute Enabled DVFS for TinyML Deployments on STM32 Microcontrollers

Autores: Elisavet Lydia Alvanaki, Manolis Katsaragakis, Dimosthenis Masouros, Sotirios Xydis, Dimitrios Soudris
Publicado en: 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2024
Editor: IEEE
DOI: 10.23919/DATE58400.2024.10546540

Differentiable Transportation Pruning

Autores: Li, Yunqiang; van Gemert, Jan C.; Hoefler, Torsten; Moons, Bert; Eleftheriou, Evangelos; Verhoef, Bram-Ernst
Publicado en: 2023 IEEE/CVF International Conference on Computer Vision (ICCV), 2023, ISSN 2380-7504
Editor: Institute of Electrical and Electronics Engineers
DOI: 10.48550/ARXIV.2307.08483

DeFiNES: Enabling Fast Exploration of the Depth-first Scheduling Space for DNN Accelerators through Analytical Modeling

Autores: Mei, Linyan; Goetschalckx, Koen; Symons, Arne; Verhelst, Marian
Publicado en: 2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2023, ISSN 2378-203X
Editor: Institute of Electrical and Electronics Engineers
DOI: 10.1109/HPCA56546.2023.10071098

Challenges and Opportunities of Security-Aware EDA

Autores: Jakob Feldtkeller; Pascal Sasdrich; Tim Güneysu
Publicado en: ACM Transactions on Embedded Computing Systems, 2023, ISSN 1539-9087
Editor: Association for Computing Machinery
DOI: 10.1145/3576199

xDSL: Sidekick Compilation for SSA-Based Compilers

Autores: Mathieu Fehr, Michel Weber, Christian Ulmann, Alexandre Lopoukhine, Martin Paul Lücke, Théo Degioanni, Christos Vasiladiotis, Michel Steuwer, Tobias Grosser
Publicado en: Proceedings of the 23rd ACM/IEEE International Symposium on Code Generation and Optimization, 2025
Editor: ACM
DOI: 10.1145/3696443.3708945

SALSA: Simulated Annealing based Loop-Ordering Scheduler for DNN Accelerators

Autores: Victor J.B. Jung, Arne Symons, Linyan Mei, Marian Verhelst, Luca Benini
Publicado en: 2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS), Edición 10168625, 2023, ISSN 2834-9857
Editor: Institute of Electrical and Electronics Engineers
DOI: 10.1109/AICAS57966.2023.10168625

PetaOps/W edge-AI Processors: Myth or reality?

Autores: Manil Dev Gomony, Floran De Putter, Anteneh Gebregiorgis, Gianna Paulin, Linyan Mei, Vikram Jain, Said Hamdioui, Victor Sanchez, Tobias Grosser, Marc Geilen, Marian Verhelst, Friedemann Zenke, Frank Gurkaynak, Barry De Bruin, Sander Stuijk, Simon Davidson
Publicado en: 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2023, ISSN 1558-1101
Editor: Institute of Electrical and Electronics Engineers
DOI: 10.23919/DATE56975.2023.10136926

Analog or Digital In-Memory Computing? Benchmarking Through Quantitative Modeling

Autores: Jiacong Sun, Pouya Houshmand, Marian Verhelst
Publicado en: 2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD), 2023, ISSN 1933-7760
Editor: Institute of Electrical and Electronics Engineers
DOI: 10.1109/ICCAD57390.2023.10323763

Towards a tailored mixed-precision sub-8-bit quantization scheme for Gated Recurrent Units using Genetic Algorithms

Autores: Riccardo Miccini, Alessandro Cerioli, Clément Laroche, Tobias Piechowiak, Jens Sparsø, Luca Pezzarossa
Publicado en: Proceedings of tinyML Research Symposium (tinyML Research Symposium’24), 2024, ISSN 2331-8422
Editor: Association for Computing Machinery
DOI: 10.48550/ARXIV.2402.12263

Gadget-based Masking of Streamlined NTRU Prime Decapsulation in Hardware

Autores: Adrian Marotzke, Georg Land, Jan Richter-Brockmann, Tim Güneysu
Publicado en: IACR Transactions on Cryptographic Hardware and Embedded Systems (CHES 2024), 2023, ISSN 2569-2925
Editor: International Association for Cryptologic Research
DOI: 10.46586/TCHES.V2024.I1.1-26

Optimising GPGPU Execution Through Runtime Micro-Architecture Parameter Analysis

Autores: Giuseppe Maria Sarda, Nimish Shah, Debjyoti Bhattacharjee, Peter Debacker, Marian Verhelst
Publicado en: 2023 IEEE INTERNATIONAL SYMPOSIUM ON WORKLOAD CHARACTERIZATION, IISWC; 2023, 2023, ISSN 2835-2238
Editor: Institute of Electrical and Electronics Engineers
DOI: 10.1109/IISWC59245.2023.00017

CELLO: Compiler-Assisted Efficient Load-Load Ordering in Data-Race-Free Regions

Autores: S Singh, J Feliu, ME Acacio, A Jimborean, A Ros
Publicado en: International Conference on Parallel Architectures and Compilation Techniques (PACT), 2023, ISBN 979-8-3503-4254-3
Editor: Institute of Electrical and Electronics Engineers
DOI: 10.1109/PACT58117.2023.00009

A Holistic Approach Towards Side-Channel Secure Fixed-Weight Polynomial Sampling

Autores: Markus Krausz, Georg Land, Jan Richter-Brockmann, Tim Güneysu
Publicado en: PKC 2023: 26th IACR International Conference on Practice and Theory of Public-Key Cryptography, 2023, ISSN 0302-9743
Editor: Public-Key Cryptography
DOI: 10.1007/978-3-031-31371-4_4

Resource-Efficient Speech Quality Prediction through Quantization Aware Training and Binary Activation Maps

Autores: Mattias Nilsson, Riccardo Miccini, Clement Laroche, Tobias Piechowiak, Friedemann Zenke
Publicado en: Interspeech 2024, 2024
Editor: ISCA
DOI: 10.21437/Interspeech.2024-1979

Free Bits: Latency Optimization of Mixed-Precision Quantized Neural Networks on the Edge

Autores: Rutishauser, Georg; Conti, Francesco; Benini, Luca
Publicado en: 2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2023, ISSN 2834-9857
Editor: Institute of Electrical and Electronics Engineers
DOI: 10.1109/AICAS57966.2023.10168577

Quantitative Fault Injection Analysis

Autores: Jakob Feldtkeller, Tim Güneysu, Patrick Schaumont
Publicado en: Advances in Cryptology – ASIACRYPT 2023, 2023, ISSN 0302-9743
Editor: Springer, Singapore
DOI: 10.1007/978-981-99-8730-6_10

Combined Private Circuits - Combined Security Refurbished

Autores: Jakob Feldtkeller, Tim Güneysu, Thorben Moos, Jan Richter-Brockmann, Sayandeep Saha, Pascal Sasdrich, François-Xavier Standaert
Publicado en: ACM Conference on Computer and Communications Security (CCS), 2023, ISSN 1543-7221
Editor: Association for Computing Machinery
DOI: 10.1145/3576915.3623129

Dynamic nsNET2: Efficient Deep Noise Suppression with Early Exiting

Autores: Miccini, Riccardo; Zniber, Alaa; Laroche, Clément; Piechowiak, Tobias; Schoeberl, Martin; Pezzarossa, Luca; Karrakchou, Ouassim; Sparsø, Jens; Ghogho, Mounir
Publicado en: IEEE International Workshop on Machine Learning for Signal Processing (MLSP 2023), 2023, ISSN 2161-0371
Editor: Institute of Electrical and Electronics Engineers
DOI: 10.1109/MLSP55844.2023.10285925

Data-driven HLS optimization for reconfigurable accelerators

Autores: Aggelos Ferikoglou, Andreas Kakolyris, Vasilis Kypriotis, Dimosthenis Masouros, Dimitrios Soudris, Sotirios Xydis
Publicado en: Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
Editor: ACM
DOI: 10.1145/3649329.3658471

Alternate Path μ-op Cache Prefetching

Autores: Sawan Singh, Arthur Perais, Alexandra Jimborean, Alberto Ros
Publicado en: 2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA), 2024
Editor: IEEE
DOI: 10.1109/ISCA59077.2024.00092

Peer reviewed articles (4)

Falcon: A Scalable Analytical Cache Model

Autores: Arjun Pitchanathan, Kunwar Grover, Tobias Grosser
Publicado en: Proceedings of the ACM on Programming Languages, Edición 8, 2024, ISSN 2475-1421
Editor: Association for Computing Machinery (ACM)
DOI: 10.1145/3656452

COAC: Cross-Layer Optimization of Accelerator Configurability for Efficient CNN Processing

Autores: Steven Colleman; Man Shi; Marian Verhelst
Publicado en: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2023, ISSN 1063-8210
Editor: Institute of Electrical and Electronics Engineers
DOI: 10.1109/TVLSI.2023.3268084

Reliable and Energy-Efficient Diabetic Retinopathy Screening Using Memristor-Based Neural Networks

Autores: Sumit Diware, Koteswararao Chilakala, Rajiv V. Joshi, Said Hamdioui, Rajendra Bishnoi
Publicado en: IEEE Access, Edición Volume 12, 2024, ISSN 2169-3536
Editor: IEEE
DOI: 10.1109/ACCESS.2024.3383014

Synthetic data generation techniques for training deep acoustic siren identification networks

Autores: Stefano Damiano; Benjamin Cramer;Andre Guntoro; Toon van Waterschoot
Publicado en: Frontiers in Signal Processing, Edición Volume 4 - 2024, 2024, ISSN 2673-8198
Editor: Frontiers
DOI: 10.3389/frsip.2024.1358532

Other (1)

Dynamic Early Exiting Predictive Coding Neural Networks

Autores: Alaa Zniber, Ouassim Karrakchou, Mounir Ghogho
Publicado en: 2024
Editor: open source
DOI: 10.48550/arXiv.2309.02022