Seamless design of smart edge processors

CORDIS fornisce collegamenti ai risultati finali pubblici e alle pubblicazioni dei progetti ORIZZONTE.

I link ai risultati e alle pubblicazioni dei progetti del 7° PQ, così come i link ad alcuni tipi di risultati specifici come dataset e software, sono recuperati dinamicamente da .OpenAIRE .

Risultati finali

Technical specification for neural accelerator hardware

Set of technical requirements for hardware accelerators for neural networks (to WP2)

Description SoC architecture, and the rapid design & prototyping environment

Report in detail the developed SoC architecture, and the first generation of the rapid design & prototyping environment useable by other partners.

Requirements, Threats, and Vulnerabilities Analysis

Description of the use cases security requirements, potential threats, and identified vulnerabilities

Intermediate Neural network resiliency analysis and AxC optimizations

Intermediate report of the NN resiliency analysis for AxC framework

Modular architecture template definition

Definition of high level SoC architecture and interfaces for accelerators, to be aligned with WP2/3.

Update of requirements and use cases

Update of D1.1 after the point demos are ready

Compiler prototype

Report and first prototype of our compiler and DSL framework, implementing constraints and opportunities in the compiler middle end. This deliverable is extended to incorporate topology-aware asymmetric CGRA arithmetic mappings;

Initial requirements and use cases

Description of the use cases, their first set of requirements and their technical specification. These are originating from all use cases on all aspects of the CONVOLVE objectives. An initial relationship between requirements and objectives to use-cases is provided.

Report on the roadmap

Definition of energy-efficient, reconfigurable, and self-healing accelerators.

Initial communication plan and reports

Initial definition of the communication plan and reporting of the communication activities carried out.

Initial Dissemination plan and report

Initial report on definition of the dissemination plan and reporting of the dissemination activities carried out

Intermediate report on the design of the targeted accelerator blocks

Definition of the micro-architecture of the targeted accelerators and design progress of the targeted accelerators.

Roadmap document for neural networks

Roadmap document for low power, high performance neural networks.

Description of the gen1 performance analysis framework and DSE framework

Report in detail the first generation of the developed performance analysis framework and DSE framework for heterogeneous ML platforms useable by other partners.

Constraints and opportunities definition

Integration design document on (security) constraints and (optimization) opportunities and compiler interface design, including interfaces with other WPs and open-source infrastructure (LLVM, MLIR).

Initial Memory management and allocation for ULP accelerators

Initial report and code of the MM customized to the CONVOLVE SoC architecture

Intermediate report on the accelerator simulator

Reporting the developed performance models and provides the progress of the simulator design to utilize the models

Pubblicazioni

Late Breaking Results: Language-level QoR modeling for High-Level Synthesis

Autori: Dimosthenis Masouros, Aggelos Ferikoglou, Georgios Zervakis, Sotirios Xydis, Dimitrios Soudris
Pubblicato in: Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
Editore: ACM
DOI: 10.1145/3649329.3663500

Energy-efficient SNN Architecture using 3nm FinFET Multiport SRAM-based CIM with Online Learning

Autori: Lucas Huijbregts; Hsiao-Hsuan Liu; Paul Detterer; Said Hamdioui; Amirreza Yousefzadeh; Rajendra Bishnoi
Pubblicato in: Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
Editore: Association for Computing Machinery
DOI: 10.48550/ARXIV.2410.09130

Multi-Partner Project: Securing Future Edge-AI Processors in Practice (CONVOLVE)

Autori: Sven Argo, Henk Corporaal, Alejandro Garza, Marc Geilen, Manil Dev Gomony, Tim Güneysu, Adrian Marotzke, Fouwad Mir, Jan Richter-Brockmann, Jeffrey Smith, Mottaqiallah Taouil, Said Hamdioui
Pubblicato in: 2025 Design, Automation &amp; Test in Europe Conference (DATE), 2025
Editore: IEEE
DOI: 10.23919/DATE64628.2025.10993210

SECOMP: Formally Secure Compilation of Compartmentalized C Programs

Autori: Jérémy Thibault, Roberto Blanco, Dongjae Lee, Sven Argo, Arthur Azevedo de Amorim, Aïna Linn Georges, Cătălin Hriţcu, Andrew Tolmach
Pubblicato in: Proceedings of the 2024 on ACM SIGSAC Conference on Computer and Communications Security, 2025
Editore: ACM
DOI: 10.1145/3658644.3670288

CMDS: Cross-layer Dataflow Optimization for DNN Accelerators Exploiting Multi-bank Memories

Autori: Man Shi; Steven Colleman MICAS-ESAT, KU Leuven ; Charlotte VanDeMieroop; Antony Joseph; Maurice Meijer; Wim Dehaene; Marian Verhelst
Pubblicato in: 2023 24th International Symposium on Quality Electronic Design (ISQED), 2023, ISSN 1948-3295
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/ISQED57927.2023.10129330

CIMple: Standard-cell SRAM-based CIM with LUT-based split softmax for attention acceleration

Autori: Bas Ahn, Xingjian Tao, Manil D. Gomony, Marc Geilen, Henk Corporaal
Pubblicato in: 2025 Cross-Disciplinary Conference on Memory-Centric Computing (CCMCC), 2026
Editore: IEEE
DOI: 10.1109/CCMCC67628.2025.11380467

Early Exiting Predictive Coding Neural Networks for Edge AI

Autori: Alaa Zniber, Mounir Ghogho, Ouassim Karrakchou, Mehdi Zakroum
Pubblicato in: 2025 33rd European Signal Processing Conference (EUSIPCO), 2025
Editore: IEEE
DOI: 10.23919/EUSIPCO63237.2025.11226813

An Empirical Evaluation of Sliding Windows on Siren Detection Task using Spiking Neural Networks

Autori: Shreya Kshirasagar; Andre Guntoro; Christian Mayr
Pubblicato in: 6th International Conference on Advances in Signal Processing and Artificial Intelligence (ASPAI' 2024), 2024, ISSN 2938-5350
Editore: International Frequency Sensor Association
DOI: 10.13140/RG.2.2.23368.53763

Improving equilibrium propagation without weight symmetry through Jacobian homeostasis

Autori: Laborieux, A. and Zenke, F.
Pubblicato in: The Twelfth International Conference on Learning Representations, 2024
Editore: ICLR 2024
DOI: 10.48550/ARXIV.2309.02214

ACCO: Automated Causal CNN Scheduling Optimizer for Real-Time Edge Accelerators

Autori: Jun Yin, Linyan Mei, Andre Guntoro, Marian Verhelst
Pubblicato in: """2023 IEEE 41st International Conference on Computer Design (ICCD) """, 2023, ISSN 2576-6996
Editore: ACM/IEEE
DOI: 10.1109/ICCD58817.2023.00065

ESAM: Energy-efficient SNN Architecture using 3nm FinFET Multiport SRAM-based CIM with Online Learning

Autori: Lucas Huijbregts, Liu Hsiao-Hsuan, Paul Detterer, Said Hamdioui, Amirreza Yousefzadeh, Rajendra Bishnoi
Pubblicato in: 2024
Editore: Proceedings of the 61st ACM/IEEE Design Automation Conference
DOI: 10.48550/arXiv.2410.09130

A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions

Autori: Alexandre Lopoukhine, Federico Ficarelli, Christos Vasiladiotis, Anton Lydike, Josse Van Delm, Alban Dutilleul, Luca Benini, Marian Verhelst, Tobias Grosser
Pubblicato in: Proceedings of the 23rd ACM/IEEE International Symposium on Code Generation and Optimization, 2025
Editore: ACM
DOI: 10.1145/3696443.3708952

DataMaestro: A Versatile and Efficient Data Streaming Engine Bringing Decoupled Memory Access To Dataflow Accelerators

Autori: Xiaoling Yi, Yunhao Deng, Ryan Antonio, Fanchen Kong, Guilherme Paim, Marian Verhelst
Pubblicato in: 2025 62nd ACM/IEEE Design Automation Conference (DAC), 2025
Editore: IEEE
DOI: 10.1109/DAC63849.2025.11133141

The PMP Snapshot Engine: Fast and Fault-Resilient PMP Reconfiguration for RISC-V

Autori: Christian Larmann, Abdullah Aljuffri, Adrian Marotzke, Alejandro Garza, Said Hamdioui, Mottaqiallah Taouil
Pubblicato in: 2026 Design, Automation &amp; Test in Europe Conference (DATE), 2026, ISSN 1558-1101
Editore: IEEE
DOI: 10.23919/DATE69613.2026.11539331

Voltage Aware Approximate CGRA Synthesis for Energy Efficient DNN Inference

Autori: Georgios Alexandris, Panagiotis Chaidos, Alexis Maras, Barry de Bruin, Manil Dev Gomony, Henk Corporaal, Dimitrios Soudris, Sotirios Xydis
Pubblicato in: 2026 Design, Automation &amp; Test in Europe Conference (DATE), 2026, ISSN 1558-1101
Editore: IEEE
DOI: 10.23919/DATE69613.2026.11539365

Dependability of Future Edge-AI Processors: Pandora’s Box

Autori: Manil Dev Gomony, Anteneh Gebregiorgis, Moritz Fieback, Marc Geilen, Sander Stuijk, Jan Richter-Brockmann, Rajendra Bishnoi, Sven Argo, Lara Arche Andradas, Tim Güneysu, Mottaqiallah Taouil, Henk Corporaal, Said Hamdioui
Pubblicato in: 2023 IEEE European Test Symposium (ETS), 2023, ISSN 1558-1780
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/ETS56758.2023.10174180

DualRes: Production-ready Dynamic Object Detection

Autori: Jibril El Hassani, Thomas Verelst
Pubblicato in: 2026
Editore: Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision (WACV) 2026
DOI: 10.1109/WACV61042.2026.00757

Optimizing Layer-Fused Scheduling of Transformer Networks on Multi-accelerator Platforms

Autori: Steven Colleman, Arne Symons, Victor J.B. Jung, Marian Verhelst
Pubblicato in: 2024 25th International Symposium on Quality Electronic Design (ISQED), 2024, ISSN 1948-3295
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/ISQED60706.2024.10528689

Auditory Anomaly Detection using Recurrent Spiking Neural Networks

Autori: Shreya Kshirasagar, Benjamin Cramer, Andre Guntoro, Christian Mayr
Pubblicato in: 2024 IEEE 6th International Conference on AI Circuits and Systems (AICAS), 2024
Editore: IEEE
DOI: 10.1109/AICAS59952.2024.10595878

Efficient Precision-Scalable Hardware for Microscaling (MX) Processing in Robotics Learning

Autori: Stef Cuyckens, Xiaoling Yi, Nitish Satya Murthy, Chao Fang, Marian Verhelst
Pubblicato in: 2025 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2025
Editore: IEEE
DOI: 10.1109/ISLPED65674.2025.11261796

ACCO: Automated Causal CNN Scheduling Optimizer for Real-Time Edge Accelerators

Autori: Jun Yin, Linyan Mei, Andre Guntoro, Marian Verhelst
Pubblicato in: 2023 IEEE 41st International Conference on Computer Design (ICCD), 2024
Editore: IEEE
DOI: 10.1109/ICCD58817.2023.00065

Verifying Peephole Rewriting In SSA Compiler IRs

Autori: Siddharth Bhat, Alex Keizer, Chris Hughes, Andres Goens and Tobias Grosser
Pubblicato in: 2024
Editore: Open Access
DOI: 10.48550/arXiv.2407.03685

Energy Cost Modelling for Optimizing Large Language Model Inference on Hardware Accelerators

Autori: Robin Geens, Man Shi, Arne Symons, Chao Fang, Marian Verhelst
Pubblicato in: 2024 IEEE 37th International System-on-Chip Conference (SOCC), 2024
Editore: IEEE
DOI: 10.1109/SOCC62300.2024.10737844

Precision-Scalable Microscaling Datapaths with Optimized Reduction Tree for Efficient NPU Integration

Autori: Stef Cuyckens, Xiaoling Yi, Robin Geens, Joren Dumoulin, Martin Wiesner, Chao Fang, Marian Verhelst
Pubblicato in: 2026 31st Asia and South Pacific Design Automation Conference (ASP-DAC), 2026
Editore: IEEE
DOI: 10.1109/ASP-DAC66049.2026.11420756

OpenGeMM: A Highly-Efficient GeMM Accelerator Generator with Lightweight RISC-V Control and Tight Memory Coupling

Autori: Xiaoling Yi, Ryan Antonio, Joren Dumoulin, Jiacong Sun, Josse Van Delm, Guilherme Pereira Paim, Marian Verhelst
Pubblicato in: Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025
Editore: ACM
DOI: 10.1145/3658617.3697652

HTVM: Efficient Neural Network Deployment On Heterogeneous TinyML Platforms

Autori: Josse Van Delm, Maarten Vandersteegen, Alessio Burrello, Giuseppe Maria Sarda, Francesco Conti, Daniele Jahier Pagliari, Luca Benini, Marian Verhelst
Pubblicato in: 2023 60th ACM/IEEE Design Automation Conference (DAC), 2024
Editore: IEEE
DOI: 10.1109/DAC56929.2023.10247664

PetaOps/W edge-AI $\mu$ Processors: Myth or reality?

Autori: Manil Dev Gomony, Floran De Putter, Anteneh Gebregiorgis, Gianna Paulin, Linyan Mei, Vikram Jain, Said Hamdioui, Victor Sanchez, Tobias Grosser, Marc Geilen, Marian Verhelst, Friedemann Zenke, Frank Gurkaynak, Barry De Bruin, Sander Stuijk, Simon Davidson, Sayandip De, Mounir Ghogho, Alexandra Jimborean, Sherif Eissa, Luca Benini, Dimitrios Soudris, Rajendra Bishnoi, Sam Ainsworth, Federico Corradi, Ouassim Karrakchou, Tim Güneysu, Henk Corporaal
Pubblicato in: 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2024, ISSN 1558-1101
Editore: IEEE
DOI: 10.23919/DATE56975.2023.10136926

LOKI: a 0.266 pJ/SOP Digital SNN Accelerator with Multi-Cycle Clock-Gated SRAM in 22 nm

Autori: Rick Luiken, Lorenzo Pes, Manil Dev Gomony, Sander Stuijk
Pubblicato in: 2026 31st Asia and South Pacific Design Automation Conference (ASP-DAC), 2026
Editore: IEEE
DOI: 10.1109/ASP-DAC66049.2026.11420301

NeuralCasting: A Front-End Compilation Infrastructure for Neural Networks

Autori: Alessandro Cerioli, Riccardo Miccini, Clément Laroche, Tobias Piechowiak, Luca Pezzarossa, Jens Sparsø, Martin Schoeberl
Pubblicato in: 2024 11th International Conference on Internet of Things: Systems, Management and Security (IOTSMS), 2024
Editore: IEEE
DOI: 10.1109/IOTSMS62296.2024.10710209

Decoupled Access-Execute Enabled DVFS for TinyML Deployments on STM32 Microcontrollers

Autori: Elisavet Lydia Alvanaki, Manolis Katsaragakis, Dimosthenis Masouros, Sotirios Xydis, Dimitrios Soudris
Pubblicato in: 2024 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE), 2024
Editore: IEEE
DOI: 10.23919/DATE58400.2024.10546540

Differentiable Transportation Pruning

Autori: Li, Yunqiang; van Gemert, Jan C.; Hoefler, Torsten; Moons, Bert; Eleftheriou, Evangelos; Verhoef, Bram-Ernst
Pubblicato in: 2023 IEEE/CVF International Conference on Computer Vision (ICCV), 2023, ISSN 2380-7504
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.48550/ARXIV.2307.08483

Enabling Automatic Compiler-Driven Vectorization of Transformers

Autori: Shreya Alladi, Alberto Ros, Alexandra Jimborean
Pubblicato in: 2026 IEEE/ACM International Symposium on Code Generation and Optimization (CGO), 2026
Editore: IEEE
DOI: 10.1109/CGO68049.2026.11395226

TreeGRNG: Binary Tree Gaussian Random Number Generator for Efficient Probabilistic AI Hardware

Autori: Jonas Crols, Guilherme Paim, Shirui Zhao, Marian Verhelst
Pubblicato in: 2024 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE), 2024
Editore: IEEE
DOI: 10.23919/DATE58400.2024.10546516

DeFiNES: Enabling Fast Exploration of the Depth-first Scheduling Space for DNN Accelerators through Analytical Modeling

Autori: Mei, Linyan; Goetschalckx, Koen; Symons, Arne; Verhelst, Marian
Pubblicato in: 2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2023, ISSN 2378-203X
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/HPCA56546.2023.10071098

Analog or Digital In-Memory Computing? Benchmarking Through Quantitative Modeling

Autori: Jiacong Sun, Pouya Houshmand, Marian Verhelst
Pubblicato in: 2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD), 2024
Editore: IEEE
DOI: 10.1109/ICCAD57390.2023.10323763

Challenges and Opportunities of Security-Aware EDA

Autori: Jakob Feldtkeller; Pascal Sasdrich; Tim Güneysu
Pubblicato in: ACM Transactions on Embedded Computing Systems, 2023, ISSN 1539-9087
Editore: Association for Computing Machinery
DOI: 10.1145/3576199

xDSL: Sidekick Compilation for SSA-Based Compilers

Autori: Mathieu Fehr, Michel Weber, Christian Ulmann, Alexandre Lopoukhine, Martin Paul Lücke, Théo Degioanni, Christos Vasiladiotis, Michel Steuwer, Tobias Grosser
Pubblicato in: Proceedings of the 23rd ACM/IEEE International Symposium on Code Generation and Optimization, 2025
Editore: ACM
DOI: 10.1145/3696443.3708945

SALSA: Simulated Annealing based Loop-Ordering Scheduler for DNN Accelerators

Autori: Victor J.B. Jung, Arne Symons, Linyan Mei, Marian Verhelst, Luca Benini
Pubblicato in: 2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS), Numero 10168625, 2023, ISSN 2834-9857
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/AICAS57966.2023.10168625

CMDS: Cross-layer Dataflow Optimization for DNN Accelerators Exploiting Multi-bank Memories

Autori: Man Shi, Steven Colleman, Charlotte VanDeMieroop, Antony Joseph, Maurice Meijer, Wim Dehaene, Marian Verhelst
Pubblicato in: 2023 24th International Symposium on Quality Electronic Design (ISQED), 2024
Editore: IEEE
DOI: 10.1109/ISQED57927.2023.10129330

AFSRAM-CIM: Adder Free SRAM-Based Digital Computation-in-Memory for BNN

Autori: Asmae El Arrassi, Mohammad Amin Yaldagard, Xingjian Tao, Taha Shahroodi, Fouwad Mir, Yashvardhan Biyani, Manil Dev Gomony, Anteneh Gebregiorgis, Rajiv Joshi, Said Hamdioui
Pubblicato in: 2024 IFIP/IEEE 32nd International Conference on Very Large Scale Integration (VLSI-SoC), 2025
Editore: IEEE
DOI: 10.1109/VLSI-SOC62099.2024.10767789

Extracting Weights of CIM-Based Neural Networks Through Power Analysis of Adder-Trees

Autori: Fouwad Jamil Mir, Abdullah Aljuffri, Said Hamdioui, Mottaqiallah Taouil
Pubblicato in: 2024 IEEE European Test Symposium (ETS), 2024
Editore: IEEE
DOI: 10.1109/ETS61313.2024.10567473

PetaOps/W edge-AI Processors: Myth or reality?

Autori: Manil Dev Gomony, Floran De Putter, Anteneh Gebregiorgis, Gianna Paulin, Linyan Mei, Vikram Jain, Said Hamdioui, Victor Sanchez, Tobias Grosser, Marc Geilen, Marian Verhelst, Friedemann Zenke, Frank Gurkaynak, Barry De Bruin, Sander Stuijk, Simon Davidson
Pubblicato in: 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2023, ISSN 1558-1101
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.23919/DATE56975.2023.10136926

Compiler-Assisted Instruction Fusion

Autori: Ravikiran Ravindranath Reddy, Sawan Singh, Arthur Perais, Alberto Ros, Alexandra Jimborean
Pubblicato in: 2026 IEEE/ACM International Symposium on Code Generation and Optimization (CGO), 2026
Editore: IEEE
DOI: 10.1109/CGO68049.2026.11394845

Implicit variance regularization in non-contrastive SSL. Advances in Neural Information Processing Systems

Autori: Halvagal, M. S., Laborieux, A., & Zenke, F.
Pubblicato in: Neurips 22023, 2023
Editore: NeurIPS 2023
DOI: 10.48550/ARXIV.2212.04858

Mixed-precision Neural Networks on RISC-V Cores: ISA extensions for Multi-Pumped Soft SIMD Operations

Autori: Giorgos Armeniakos, Alexis Maras, Sotirios Xydis, Dimitrios Soudris
Pubblicato in: Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2025
Editore: ACM
DOI: 10.1145/3676536.3676840

Analog or Digital In-Memory Computing? Benchmarking Through Quantitative Modeling

Autori: Jiacong Sun, Pouya Houshmand, Marian Verhelst
Pubblicato in: 2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD), 2023, ISSN 1933-7760
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/ICCAD57390.2023.10323763

Enabling Efficient Hardware Acceleration of Hybrid Vision Transformer (ViT) Networks at the Edge

Autori: Joren Dumoulin, Pouya Houshmand, Vikram Jain, Marian Verhelst
Pubblicato in: 2024 IEEE International Symposium on Circuits and Systems (ISCAS), 2024
Editore: IEEE
DOI: 10.1109/ISCAS58744.2024.10558587

Towards a tailored mixed-precision sub-8-bit quantization scheme for Gated Recurrent Units using Genetic Algorithms

Autori: Riccardo Miccini, Alessandro Cerioli, Clément Laroche, Tobias Piechowiak, Jens Sparsø, Luca Pezzarossa
Pubblicato in: Proceedings of tinyML Research Symposium (tinyML Research Symposium’24), 2024, ISSN 2331-8422
Editore: Association for Computing Machinery
DOI: 10.48550/ARXIV.2402.12263

Correction Fault Attacks on Randomized CRYSTALS-Dilithium

Autori: Elisabeth Krahmer; Peter Pessl; Georg Land; Tim Güneysu
Pubblicato in: IACR Transactions on Cryptographic Hardware and Embedded Systems, 2024
Editore: Diamond Open Access
DOI: 10.46586/TCHES.V2024.I3.174-199

Gadget-based Masking of Streamlined NTRU Prime Decapsulation in Hardware

Autori: Adrian Marotzke, Georg Land, Jan Richter-Brockmann, Tim Güneysu
Pubblicato in: IACR Transactions on Cryptographic Hardware and Embedded Systems (CHES 2024), 2023, ISSN 2569-2925
Editore: International Association for Cryptologic Research
DOI: 10.46586/TCHES.V2024.I1.1-26

From Diet to Free Lunch: Estimating Auxiliary Signal Properties Using Dynamic Pruning Masks in Speech Enhancement Networks

Autori: Riccardo Miccini, Clément Laroche, Tobias Piechowiak, Xenofon Fafoutis, Luca Pezzarossa
Pubblicato in: ICASSP 2026 - 2026 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 2026
Editore: IEEE
DOI: 10.1109/ICASSP55912.2026.11463996

Optimising GPGPU Execution Through Runtime Micro-Architecture Parameter Analysis

Autori: Giuseppe Maria Sarda, Nimish Shah, Debjyoti Bhattacharjee, Peter Debacker, Marian Verhelst
Pubblicato in: 2023 IEEE INTERNATIONAL SYMPOSIUM ON WORKLOAD CHARACTERIZATION, IISWC; 2023, 2023, ISSN 2835-2238
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/IISWC59245.2023.00017

CELLO: Compiler-Assisted Efficient Load-Load Ordering in Data-Race-Free Regions

Autori: S Singh, J Feliu, ME Acacio, A Jimborean, A Ros
Pubblicato in: International Conference on Parallel Architectures and Compilation Techniques (PACT), 2023, ISBN 979-8-3503-4254-3
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/PACT58117.2023.00009

A Holistic Approach Towards Side-Channel Secure Fixed-Weight Polynomial Sampling

Autori: Markus Krausz, Georg Land, Jan Richter-Brockmann, Tim Güneysu
Pubblicato in: PKC 2023: 26th IACR International Conference on Practice and Theory of Public-Key Cryptography, 2023, ISSN 0302-9743
Editore: Public-Key Cryptography
DOI: 10.1007/978-3-031-31371-4_4

Time-Predictable Deep Noise Suppression on an Edge Device

Autori: Alessandro Cerioli, Tórur Biskopstø Strøm, Clément Laroche, Tobias Piechowiak, Luca Pezzarossa, Martin Schoeberl
Pubblicato in: 2025 28th International Symposium on Real-Time Distributed Computing (ISORC), 2025
Editore: IEEE
DOI: 10.1109/ISORC65339.2025.00062

An Open-Source HW-SW Co-Development Framework Enabling Efficient Multi-Accelerator Systems

Autori: Ryan Albert Antonio, Joren Dumoulin, Xiaoling Yi, Josse Van Delm, Yunhao Deng, Guilherme Paim, Marian Verhelst
Pubblicato in: 2025 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2025
Editore: IEEE
DOI: 10.1109/ISLPED65674.2025.11261784

Scalable Speech Enhancement With Dynamic Channel Pruning

Autori: Riccardo Miccini, Clément Laroche, Tobias Piechowiak, Luca Pezzarossa
Pubblicato in: ICASSP 2025 - 2025 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 2025
Editore: IEEE
DOI: 10.1109/ICASSP49660.2025.10889876

The Configuration Wall: Characterization and Elimination of Accelerator Configuration Overhead

Autori: Josse Van Delm, Anton Lydike, Joren Dumoulin, Jonas Crols, Xiaoling Yi, Ryan Antonio, Jackson Woodruff, Tobias Grosser, Marian Verhelst
Pubblicato in: Proceedings of the 31st ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 1, 2025
Editore: ACM
DOI: 10.1145/3760250.3762225

Performance Modeling & Mapping of LLM Inference on Heterogeneous Vectorized CGRAs

Autori: Dionysios Kefallinos, Georgios Alexandris, Alexis Maras, Panagiotis Chaidos, Manil Dev Gomony, Henk Corporaal, Dimitrios Soudris, and Sotirios Xydis
Pubblicato in: PARMA-DITAM 2026, 2026
Editore: Open Access Series in Informatics (OASIcs)
DOI: 10.4230/OASICS.PARMA-DITAM.2026.8

Efficient Streaming Speech Quality Prediction with Spiking Neural Networks

Autori: Mattias Nilsson, Riccardo Miccini, Julian Rossbroich, Clément Laroche, Tobias Piechowiak, Friedemann Zenke
Pubblicato in: Interspeech 2025, 2025
Editore: ISCA
DOI: 10.21437/INTERSPEECH.2025-2269

Resource-Efficient Speech Quality Prediction through Quantization Aware Training and Binary Activation Maps

Autori: Mattias Nilsson, Riccardo Miccini, Clement Laroche, Tobias Piechowiak, Friedemann Zenke
Pubblicato in: Interspeech 2024, 2024
Editore: ISCA
DOI: 10.21437/Interspeech.2024-1979

SALSA: Simulated Annealing based Loop-Ordering Scheduler for DNN Accelerators

Autori: Victor J.B. Jung, Arne Symons, Linyan Mei, Marian Verhelst, Luca Benini
Pubblicato in: 2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2024, ISSN 2834-9857
Editore: IEEE
DOI: 10.1109/AICAS57966.2023.10168625

Decoding Finger Velocity from Cortical Spike Trains with Recurrent Spiking Neural Networks

Autori: Tengjun Liu, Julia Gygax, Julian Rossbroich, Yansong Chua, Shaomin Zhang, Friedemann Zenke
Pubblicato in: 2024 IEEE Biomedical Circuits and Systems Conference (BioCAS), 2024
Editore: IEEE
DOI: 10.1109/BIOCAS61083.2024.10798222

Fine-Grained Fusion: The Missing Piece in Area-Efficient State Space Model Acceleration

Autori: Robin Geens, Arne Symons, Marian Verhelst
Pubblicato in: 2025 34th International Conference on Parallel Architectures and Compilation Techniques (PACT), 2025
Editore: IEEE
DOI: 10.1109/PACT65351.2025.00034

Free Bits: Latency Optimization of Mixed-Precision Quantized Neural Networks on the Edge

Autori: Rutishauser, Georg; Conti, Francesco; Benini, Luca
Pubblicato in: 2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2023, ISSN 2834-9857
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/AICAS57966.2023.10168577

Adaptive Slimming for Scalable and Efficient Speech Enhancement

Autori: Riccardo Miccini, Minje Kim, Clément Laroche, Luca Pezzarossa, Paris Smaragdis
Pubblicato in: 2025 IEEE Workshop on Applications of Signal Processing to Audio and Acoustics (WASPAA), 2025
Editore: IEEE
DOI: 10.1109/WASPAA66052.2025.11230950

Quantitative Fault Injection Analysis

Autori: Jakob Feldtkeller, Tim Güneysu, Patrick Schaumont
Pubblicato in: Advances in Cryptology – ASIACRYPT 2023, 2023, ISSN 0302-9743
Editore: Springer, Singapore
DOI: 10.1007/978-981-99-8730-6_10

Combined Private Circuits - Combined Security Refurbished

Autori: Jakob Feldtkeller, Tim Güneysu, Thorben Moos, Jan Richter-Brockmann, Sayandeep Saha, Pascal Sasdrich, François-Xavier Standaert
Pubblicato in: ACM Conference on Computer and Communications Security (CCS), 2023, ISSN 1543-7221
Editore: Association for Computing Machinery
DOI: 10.1145/3576915.3623129

Dynamic nsNET2: Efficient Deep Noise Suppression with Early Exiting

Autori: Miccini, Riccardo; Zniber, Alaa; Laroche, Clément; Piechowiak, Tobias; Schoeberl, Martin; Pezzarossa, Luca; Karrakchou, Ouassim; Sparsø, Jens; Ghogho, Mounir
Pubblicato in: IEEE International Workshop on Machine Learning for Signal Processing (MLSP 2023), 2023, ISSN 2161-0371
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/MLSP55844.2023.10285925

Collaborative P4-SDN DDoS Detection and Mitigation with Early-Exit Neural Networks

Autori: Ouassim Karrakchou, Alaa Zniber, Anass Sebbar, Mounir Ghogho
Pubblicato in: GLOBECOM 2025 - 2025 IEEE Global Communications Conference, 2026
Editore: IEEE
DOI: 10.1109/GLOBECOM59602.2025.11431920

A Bespoke Design Approach to Low-Power Printed Microprocessors for Machine Learning Applications

Autori: Panagiotis Chaidos, Giorgos Armeniakos, Sotirios Xydis, Dimitrios Soudris
Pubblicato in: 2025 IEEE International Symposium on Circuits and Systems (ISCAS), 2025
Editore: IEEE
DOI: 10.1109/ISCAS56072.2025.11044307

XDMA: A Distributed, Extensible DMA Architecture for Layout-Flexible Data Movements in Heterogeneous Multi-Accelerator SoCs

Autori: Fanchen Kong, Yunhao Deng, Xiaoling Yi, Ryan Antonio, Marian Verhelst
Pubblicato in: 2025 IEEE 43rd International Conference on Computer Design (ICCD), 2025
Editore: IEEE
DOI: 10.1109/ICCD65941.2025.00104

Data-driven HLS optimization for reconfigurable accelerators

Autori: Aggelos Ferikoglou, Andreas Kakolyris, Vasilis Kypriotis, Dimosthenis Masouros, Dimitrios Soudris, Sotirios Xydis
Pubblicato in: Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
Editore: ACM
DOI: 10.1145/3649329.3658471

Alternate Path μ-op Cache Prefetching

Autori: Sawan Singh, Arthur Perais, Alexandra Jimborean, Alberto Ros
Pubblicato in: 2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA), 2024
Editore: IEEE
DOI: 10.1109/ISCA59077.2024.00092

HAETAE: Shorter Lattice-Based Fiat-Shamir Signatures

Autori: Jung Hee Cheon; Hyeongmin Choe; Julien Devevey; Tim Güneysu; Dongyeon Hong; Markus Krausz; Georg Land; Marc Möller; Damien Stehlé; MinJune Yi
Pubblicato in: IACR Transactions on Cryptographic Hardware and Embedded Systems, 2024
Editore: International Association for Cryptologic Research (IACR)
DOI: 10.46586/TCHES.V2024.I3.25-75

Flexible Hardware Accelerators for Ultra-Low Power Edge AI: The CONVOLVE Approach

Autori: Panagiotis Chaidos, Alexios Maras, Georgios Alexandris, null Xiaoling, Asmae El Arrassi, Bas Ahn, James D. Garside, Yunhao Deng, Theofilos Spyrou, Anteneh Gebregiorgis, Mottaqiallah Taouil, Manil Dev Gomony, Sotirios Xydis, Marian Verhelst, Said Hamdioui, Dimitrios Soudris, Henk Corporaal
Pubblicato in: 2025 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2025
Editore: IEEE
DOI: 10.1109/ISVLSI65124.2025.11130251

Optimizing Layer-Fused Scheduling of Transformer Networks on Multi-accelerator Platforms

Autori: Steven Colleman; Arne Symons; Victor J. B. Jung; Marian Verhelst
Pubblicato in: 2024 25th International Symposium on Quality Electronic Design (ISQED), 2024, ISSN 1948-3295
Editore: IEEE
DOI: 10.48550/ARXIV.2406.09804

Falcon: A Scalable Analytical Cache Model

Autori: Arjun Pitchanathan, Kunwar Grover, Tobias Grosser
Pubblicato in: Proceedings of the ACM on Programming Languages, Numero 8, 2024, ISSN 2475-1421
Editore: Association for Computing Machinery (ACM)
DOI: 10.1145/3656452

Efficient Precision-Scalable Hardware for Microscaling (MX) Processing in Robotics Learning

Autori: Cuyckens, Stef; Yi, Xiaoling; Satya Murthy, Nitish; Fang, Chao; Verhelst, Marian
Pubblicato in: 2025 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2025, ISSN 1558-111X
Editore: IEEE
DOI: 10.48550/ARXIV.2505.22404

EFLOP: A Sparsity-Aware Metric for Evaluating Computational Cost in Spiking and Non-Spiking Neural Networks

Autori: Simon Narduzzi, Friedemann Zenke, Shih-Chii Liu, Liza Andrea Dunbar
Pubblicato in: Neuromorphic Computing and Engineering, 2025, ISSN 2634-4386
Editore: IOP Publishing
DOI: 10.1088/2634-4386/ADDEE8

Toward Attention-Based TinyML: A Heterogeneous Accelerated Architecture and Automated Deployment Flow

Autori: Philip Wiese; Gamze Islamoglu; Moritz Scherer 0001; Luka Macan; Victor Jean-Baptiste Jung; Alessio Burrello; Francesco Conti 0001; Luca Benini
Pubblicato in: IEEE Design & Test, 2025, ISSN 2168-2364
Editore: IEEE
DOI: 10.48550/ARXIV.2408.02473

COAC: Cross-Layer Optimization of Accelerator Configurability for Efficient CNN Processing

Autori: Steven Colleman; Man Shi; Marian Verhelst
Pubblicato in: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2023, ISSN 1063-8210
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/TVLSI.2023.3268084

On-Sensor Printed Machine Learning Classification via Bespoke ADC and Decision Tree Co-Design

Autori: Giorgos Armeniakos; Paula L. Duarte; Priyanjana Pal; Georgios Zervakis 0001; Mehdi B. Tahoori; Dimitrios Soudris
Pubblicato in: 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2024, ISSN 1558-1101
Editore: IEEE
DOI: 10.48550/ARXIV.2312.01172

DREAM-CIM: A Digital SRAM-Based CIM Accelerator for Energy- and Area-Efficient Edge AI

Autori: Asmae El Arrassi, Lucas Huijbregts, Manil Dev Gomony, Anteneh Gebregiorgis, Francky Catthoor, Mottaqiallah Taouil, Rajiv Joshi, Said Hamdioui
Pubblicato in: IEEE Transactions on Circuits and Systems for Artificial Intelligence, Numero 2, 2025, ISSN 2996-6647
Editore: Institute of Electrical and Electronics Engineers (IEEE)
DOI: 10.1109/TCASAI.2025.3579709

Dependability of Future Edge-AI Processors: Pandora’s Box

Autori: Manil Dev Gomony; Anteneh Gebregiorgis; Moritz Fieback; Marc Geilen; Sander Stuijk; Jan Richter-Brockmann; Rajendra Bishnoi; Sven Argo; Lara Arche Andradas; Tim Güneysu; Mottaqiallah Taouil; Henk Corporaal; Said Hamdioui
Pubblicato in: 2023 IEEE European Test Symposium (ETS), 2023, ISSN 1558-1780
Editore: IEEE
DOI: 10.1109/ETS56758.2023.10174180

Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC With 2–8 b DNN Acceleration and 30%-Boost Adaptive Body Biasing

Autori: Francesco Conti, Gianna Paulin, Angelo Garofalo, Davide Rossi, Alfio Di Mauro, Georg Rutishauser, Gianmarco Ottavi, Manuel Eggiman, Hayate Okuhara, Luca Benini
Pubblicato in: IEEE Journal of Solid-State Circuits, Numero 59, 2025, ISSN 0018-9200
Editore: Institute of Electrical and Electronics Engineers (IEEE)
DOI: 10.1109/JSSC.2023.3318301

MaRVIn: A Cross-Layer Mixed-Precision RISC-V Framework for DNN Inference, from ISA Extension to Hardware Acceleration

Autori: Giorgos Armeniakos, Alexis Maras, Sotirios Xydis, Dimitrios Soudris
Pubblicato in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2025, ISSN 0278-0070
Editore: Institute of Electrical and Electronics Engineers (IEEE)
DOI: 10.1109/TCAD.2025.3615505

Memristor-Based Lightweight Encryption

Autori: Siddiqi, Muhammad Ali; Galvan Hernández, Jan Andrés; Gebreziorgis, Anteneh; Bishnoi, Rajendra; Strydis, Christos; Hamdioui, Said; Taouil, Mottaqiallah
Pubblicato in: 2023 26th Euromicro Conference on Digital System Design (DSD), 2023, ISSN 2771-2508
Editore: IEEE
DOI: 10.48550/ARXIV.2404.00125

TransAxx: Efficient Transformers With Approximate Computing

Autori: Dimitrios Danopoulos; Georgios Zervakis; Dimitrios Soudris; Jörg Henkel
Pubblicato in: IEEE Transactions on Circuits and Systems for Artificial Intelligence, 2025, ISSN 2996-6647
Editore: IEEE
DOI: 10.48550/ARXIV.2402.07545

Accelerating TinyML Inference on Microcontrollers Through Approximate Kernels

Autori: Giorgos Armeniakos; Georgios Mentzos; Dimitrios Soudris
Pubblicato in: 2024 31st IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2024, ISSN 2995-0589
Editore: IEEE
DOI: 10.1109/ICECS61496.2024.10848979

Leveraging edge artificial intelligence for sustainable agriculture

Autori: El Jarroudi, Moussa; Kouadio, Amani Louis; Delfosse, Philippe; Bock, Clive H.; Mahlein, Anne-Katrin; Fettweis, Xavier; Mercatoris, Benoît; Adams, Frank; Lenné, Jillian M.; Hamdioui, Said
Pubblicato in: Nature Sustainability, 2024, ISSN 2398-9629
Editore: Nature Sustainability
DOI: 10.1038/S41893-024-01352-4

Hardware‐Centric Analysis of DeepSeek's Multi‐Head Latent Attention

Autori: Robin Geens, Marian Verhelst
Pubblicato in: Electronics Letters, Numero 61, 2026, ISSN 0013-5194
Editore: Institution of Engineering and Technology (IET)
DOI: 10.1049/ELL2.70504

Stream: Design Space Exploration of Layer-Fused DNNs on Heterogeneous Dataflow Accelerators

Autori: Arne Symons; Linyan Mei; Steven Colleman; Pouya Houshmand; Sebastian Karl; Marian Verhelst
Pubblicato in: IEEE Transactions on Computers, 2025, ISSN 1557-9956
Editore: IEEE
DOI: 10.48550/ARXIV.2212.10612

Deeploy: Enabling Energy-Efficient Deployment of Small Language Models on Heterogeneous Microcontrollers

Autori: Moritz Scherer, Luka Macan, Victor J. B. Jung, Philip Wiese, Luca Bompani, Alessio Burrello, Francesco Conti, Luca Benini
Pubblicato in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Numero 43, 2024, ISSN 0278-0070
Editore: Institute of Electrical and Electronics Engineers (IEEE)
DOI: 10.1109/TCAD.2024.3443718

Reliable and Energy-Efficient Diabetic Retinopathy Screening Using Memristor-Based Neural Networks

Autori: Sumit Diware, Koteswararao Chilakala, Rajiv V. Joshi, Said Hamdioui, Rajendra Bishnoi
Pubblicato in: IEEE Access, Numero Volume 12, 2024, ISSN 2169-3536
Editore: IEEE
DOI: 10.1109/ACCESS.2024.3383014

First-Class Verification Dialects for MLIR

Autori: Mathieu Fehr, Yuyou Fan, Hugo Pompougnac, John Regehr, Tobias Grosser
Pubblicato in: Proceedings of the ACM on Programming Languages, Numero 9, 2025, ISSN 2475-1421
Editore: Association for Computing Machinery (ACM)
DOI: 10.1145/3729309

AIMC Modeling and Parameter Tuning for Layer-Wise Optimal Operating Point in DNN Inference

Autori: Iman Dadras, Giuseppe M. Sarda, Nathan Laubeuf, Debjyoti Bhattacharjee, Arindam Mallik
Pubblicato in: IEEE Access, Numero 11, 2023, ISSN 2169-3536
Editore: Institute of Electrical and Electronics Engineers (IEEE)
DOI: 10.1109/ACCESS.2023.3305432

Distributed Inference with Minimal Off-Chip Traffic for Transformers on Low-Power MCUs

Autori: Bochem, Severin; Jung, Victor J. B.; Prasad, Arpan Suravi; Conti, Francesco; Benini, Luca
Pubblicato in: 2025 Design, Automation & Test in Europe Conference (DATE), 2025, ISSN 1558-1101
Editore: IEEE
DOI: 10.48550/ARXIV.2412.04372

Certified Decision Procedures for Width-Independent Bitvector Predicates

Autori: Siddharth Bhat, Léo Stefanesco, Chris Hughes, Tobias Grosser
Pubblicato in: Proceedings of the ACM on Programming Languages, Numero 9, 2025, ISSN 2475-1421
Editore: Association for Computing Machinery (ACM)
DOI: 10.1145/3763148

Decoupled Access-Execute Enabled DVFS for TinyML Deployments on STM32 Microcontrollers

Autori: Alvanaki, Elisavet Lydia; Katsaragakis, Manolis; Masouros, Dimosthenis; Xydis, Sotirios; Soudris, Dimitrios
Pubblicato in: 2024 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE), 2024, ISSN 1558-1101
Editore: IEEE
DOI: 10.48550/ARXIV.2407.03711

MemPool: A Scalable Manycore Architecture With a Low-Latency Shared L1 Memory

Autori: Samuel Riedel; Matheus A. Cavalcante; Renzo Andri; Luca Benini
Pubblicato in: IEEE Transactions on Computers, 2023, ISSN 1557-9956
Editore: IEEE
DOI: 10.3929/ETHZ-B-000643341

Synthetic data generation techniques for training deep acoustic siren identification networks

Autori: Stefano Damiano; Benjamin Cramer;Andre Guntoro; Toon van Waterschoot
Pubblicato in: Frontiers in Signal Processing, Numero Volume 4 - 2024, 2024, ISSN 2673-8198
Editore: Frontiers
DOI: 10.3389/frsip.2024.1358532

Interactive Bitvector Reasoning using Verified Bit-Blasting

Autori: Henrik Böving, Siddharth Bhat, Luisa Cicolini, Alex Keizer, Léon Frenot, Abdalrhman Mohamed, Léo Stefanesco, Harun Khan, Joshua Clune, Clark Barrett, Tobias Grosser
Pubblicato in: Proceedings of the ACM on Programming Languages, Numero 9, 2025, ISSN 2475-1421
Editore: Association for Computing Machinery (ACM)
DOI: 10.1145/3763167

Stream: Design Space Exploration of Layer-Fused DNNs on Heterogeneous Dataflow Accelerators

Autori: Arne Symons, Linyan Mei, Steven Colleman, Pouya Houshmand, Sebastian Karl, Marian Verhelst
Pubblicato in: IEEE Transactions on Computers, Numero 74, 2025, ISSN 0018-9340
Editore: Institute of Electrical and Electronics Engineers (IEEE)
DOI: 10.1109/TC.2024.3477938

Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality With At-MRAM Neural Engine

Autori: Arpan Suravi Prasad; Moritz Scherer 0001; Francesco Conti 0001; Davide Rossi 0001; Alfio Di Mauro; Manuel Eggimann; Jorge Tomás Gómez; Ziyun Li 0001; Syed Shakib Sarwar; Zhao Wang; Barbara De Salvo; Luca Benini
Pubblicato in: IEEE Journal of Solid-State Circuits, 2024, ISSN 1558-173X
Editore: IEEE
DOI: 10.48550/ARXIV.2312.14750

<i>FlexiGen</i> : An Automated AI Accelerator Generation Framework With Decoupled-Access-Execute and Dynamic Dataflows

Autori: Xiaoling Yi, Man Shi, Joren Dumoulin, Jiacong Sun, Yunhao Deng, Ryan Antonio, Fanchen Kong, Yu Zhang, Yuqi Jiang, Marian Verhelst
Pubblicato in: IEEE Transactions on Circuits and Systems I: Regular Papers, 2026, ISSN 1549-8328
Editore: Institute of Electrical and Electronics Engineers (IEEE)
DOI: 10.1109/TCSI.2026.3669425

Dynamic Early Exiting Predictive Coding Neural Networks

Autori: Alaa Zniber, Ouassim Karrakchou, Mounir Ghogho
Pubblicato in: 2024
Editore: open source
DOI: 10.48550/arXiv.2309.02022

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