Periodic Reporting for period 1 - PUNCH (Packaging of novel Ultra-dyNamiC pHotonic switches and transceivers for integration into 5G radio access network and datacenter sub-systems)
Période du rapport: 2022-09-01 au 2024-02-29
The increasing demands for emerging high-volume and latency-constrained applications, such as artificial intelligence, autonomous vehicles, and augmented/virtual reality, are imposing stringent requirements on data center network capacity, latency, energy consumption, and guaranteed delivery. Current data center interconnects with static node configurations are being pushed to their limits by the diverse demands of this set of applications. Flexible architectures that match their capacity to an application's traffic pattern can deliver optimized connectivity while eliminating over-provisioned resources. Transparent optical switches are the key enablers. However, as short-reach interconnects approach petabit-scale capacity with massively parallel wavelengths, switching at the wavelength granularity is becoming vital.
The multi-dimensional switch developed within PUNCH offers reconfigurable interconnects from all-to-all links, to imbalanced group-to-group traffic by bandwidth steering. A space-and-wavelength switch fabric forms the core for arbitrarily routing any combination of wavelengths from any input to any output. An extra key lies in the ultra-fast reconfigurability, which is a cornerstone that enables unparalleled dynamics by multiplexing in the time domain. The combination of photonic switching in the space, wavelength and time domains holds great promise for agile, adaptive, and deterministic data center networks.
To ensure low cost per port, optical switching technologies must demonstrate a path towards high-volume manufacturing. Silicon photonics has been identified as a key enabling technology, providing a high-level of integration and compatibility with CMOS processes. However, large-scale switch fabrics pose huge challenges in terms of optical and electrical packaging. Furthermore, insertion loss is limiting commercial uptake, motivating the integration of semiconductor optical amplifiers (SOA) to provide on-chip gain.
Within PUNCH, full thermal, electrical, and optical packaging solutions are incorporated, leveraging semiconductor packaging technology compatible with high-volume manufacturing. The development of a III-V foundry process for micro-transfer-printing compatible semiconductor optical amplifiers enables lossless optical switching on the silicon photonics platform. Custom designed electronic ICs to actuate, control, and power-monitor scaled switch fabrics are densely integrated with the photonic ICs into a heterogeneous fanout wafer-level package (FOWLP), processed on a 200 mm reconstructed wafer platform. In addition, the optical interfacing to the photonic ICs is accomplished using an optical redistribution layer, providing an optical fanout on organic IC-substrates, and allowing for a scalable optical fiber packaging solution.
The novel integration and packaging processes will also be applied for manufacturing optical transceivers providing the interface between optical switches and electronic resources (compute, memory, and storage). Finally, the optical switch and transceiver prototypes will be demonstrated in a 5G RAN Transport Network, for Time-Sensitive Networking Fronthaul applications and for memory disaggregation in data centers.
The multi-dimensional switch developed within PUNCH offers reconfigurable interconnects from all-to-all links, to imbalanced group-to-group traffic by bandwidth steering. A space-and-wavelength switch fabric forms the core for arbitrarily routing any combination of wavelengths from any input to any output. An extra key lies in the ultra-fast reconfigurability, which is a cornerstone that enables unparalleled dynamics by multiplexing in the time domain. The combination of photonic switching in the space, wavelength and time domains holds great promise for agile, adaptive, and deterministic data center networks.
To ensure low cost per port, optical switching technologies must demonstrate a path towards high-volume manufacturing. Silicon photonics has been identified as a key enabling technology, providing a high-level of integration and compatibility with CMOS processes. However, large-scale switch fabrics pose huge challenges in terms of optical and electrical packaging. Furthermore, insertion loss is limiting commercial uptake, motivating the integration of semiconductor optical amplifiers (SOA) to provide on-chip gain.
Within PUNCH, full thermal, electrical, and optical packaging solutions are incorporated, leveraging semiconductor packaging technology compatible with high-volume manufacturing. The development of a III-V foundry process for micro-transfer-printing compatible semiconductor optical amplifiers enables lossless optical switching on the silicon photonics platform. Custom designed electronic ICs to actuate, control, and power-monitor scaled switch fabrics are densely integrated with the photonic ICs into a heterogeneous fanout wafer-level package (FOWLP), processed on a 200 mm reconstructed wafer platform. In addition, the optical interfacing to the photonic ICs is accomplished using an optical redistribution layer, providing an optical fanout on organic IC-substrates, and allowing for a scalable optical fiber packaging solution.
The novel integration and packaging processes will also be applied for manufacturing optical transceivers providing the interface between optical switches and electronic resources (compute, memory, and storage). Finally, the optical switch and transceiver prototypes will be demonstrated in a 5G RAN Transport Network, for Time-Sensitive Networking Fronthaul applications and for memory disaggregation in data centers.
We have successfully completed the designs for both electro-optic and thermo-optic switches, adhering to 400G-LR8 and CW-WDM MSA standards. Layouts for a 4x4x8λ thermo-optic switch fabric and for a 1x2x4λ electro-optic switching element were completed. Currently, we are awaiting the fabricated photonic integrated circuits. Ongoing efforts include designs to accommodate all wavelength channels of 400G-LR8 and simulations for topological exploration on non-blocking 8x8x8λ and 16x16x8λ switch fabrics with neutral net insertion loss.
The SOA design and fabrication process flow was developed and all the necessary preparation and development loops of the electron-beam lithography were finalized. The developed SOA design covers the identified KPIs, i.e. it enables a wideband amplification (>75 nm) of up to 10-15 dB at 70C with low crosstalk between the lines.
The required functionality and specifications for the optical switch driver have been agreed between the partners, focusing primarily on the accurate actuation of optical switch elements. The design has started, and a suitable process technology was selected.
In preparation for the integration of the functional PICs and EICs that will be available in a later stage of the project, different integration experiments have been defined, based on dedicated test chips. One of these experiments is the fabrication of representative Fan-out Wafer Level Packaging (FOWLP) samples. The layout of these packages includes a larger Si die, resembling the switch or transceiver PIC, and 8 smaller Si dies, resembling the switch control or transceiver EICs. In a face-down mold-first process, the dies have been assembled on a temporary carrier and encapsulated by compression molding with a 200 mm cavity. The processing of 2-layer electrical redistribution (RDL) with under bump metallization is ongoing.
Silicon photonics edge couplers providing mode expansion to a substrate-integrated optical redistribution layer (ORDL) based on polymer optical waveguides have been developed. This included the optical co-design of adiabatic tapers and polymer waveguides for both a silicon and a silicon nitride based platform. While Si will be used for the functional PICs, SiN allows for short-loop fabrication of test PICs, to be used for packaging process development. Fabricated SiN PICs have been successfully integrated with ORDL, and coupling efficiency has been evaluated better than -1.5 dB over the entire O-band.
The design of high-density organic substrates compatible with the assembly of fanout packages with integrated test chips started. Two different approaches for integration are being developed. The first concept is based on soldering the fanout package to the substrate, while the second concept is based on embedding the fanout package within the substrate.
For the optical coupling between fiber arrays and PICs, several approaches are under study, with and without ORDL. First functional project prototypes will be based on the use of either a single-mode fiber array with a spot size converter, or an ultra-high numerical aperture fiber array with a smaller mode field diameter. Both options will be examined based on their optical coupling efficiency (target efficiency of -1 dB) and mechanical stability. Once the ORDL is more mature, fiber coupling with an intermediate ORDL will be used.
The high-level design of the 1.6 Tb/s optical transceiver architecture has been completed, and is based on 4 spatial channels each carrying 8 wavelengths modulated with a 56Gb/s NRZ signal (based on ring resonator modulators and integrated Ge photodiodes). The design and layout of the transceiver PIC is completed, fabrication is ongoing, and PICs are expected in December 2024. The development of 4-channel modulator driver and 4-channel transimpedance amplifier EICs is ongoing. To achieve the necessary speed and low power consumption, a 28 nm CMOS process was selected. The design and layout of the Tx EIC is completed, while the design of the Rx EIC is still ongoing.
The SOA design and fabrication process flow was developed and all the necessary preparation and development loops of the electron-beam lithography were finalized. The developed SOA design covers the identified KPIs, i.e. it enables a wideband amplification (>75 nm) of up to 10-15 dB at 70C with low crosstalk between the lines.
The required functionality and specifications for the optical switch driver have been agreed between the partners, focusing primarily on the accurate actuation of optical switch elements. The design has started, and a suitable process technology was selected.
In preparation for the integration of the functional PICs and EICs that will be available in a later stage of the project, different integration experiments have been defined, based on dedicated test chips. One of these experiments is the fabrication of representative Fan-out Wafer Level Packaging (FOWLP) samples. The layout of these packages includes a larger Si die, resembling the switch or transceiver PIC, and 8 smaller Si dies, resembling the switch control or transceiver EICs. In a face-down mold-first process, the dies have been assembled on a temporary carrier and encapsulated by compression molding with a 200 mm cavity. The processing of 2-layer electrical redistribution (RDL) with under bump metallization is ongoing.
Silicon photonics edge couplers providing mode expansion to a substrate-integrated optical redistribution layer (ORDL) based on polymer optical waveguides have been developed. This included the optical co-design of adiabatic tapers and polymer waveguides for both a silicon and a silicon nitride based platform. While Si will be used for the functional PICs, SiN allows for short-loop fabrication of test PICs, to be used for packaging process development. Fabricated SiN PICs have been successfully integrated with ORDL, and coupling efficiency has been evaluated better than -1.5 dB over the entire O-band.
The design of high-density organic substrates compatible with the assembly of fanout packages with integrated test chips started. Two different approaches for integration are being developed. The first concept is based on soldering the fanout package to the substrate, while the second concept is based on embedding the fanout package within the substrate.
For the optical coupling between fiber arrays and PICs, several approaches are under study, with and without ORDL. First functional project prototypes will be based on the use of either a single-mode fiber array with a spot size converter, or an ultra-high numerical aperture fiber array with a smaller mode field diameter. Both options will be examined based on their optical coupling efficiency (target efficiency of -1 dB) and mechanical stability. Once the ORDL is more mature, fiber coupling with an intermediate ORDL will be used.
The high-level design of the 1.6 Tb/s optical transceiver architecture has been completed, and is based on 4 spatial channels each carrying 8 wavelengths modulated with a 56Gb/s NRZ signal (based on ring resonator modulators and integrated Ge photodiodes). The design and layout of the transceiver PIC is completed, fabrication is ongoing, and PICs are expected in December 2024. The development of 4-channel modulator driver and 4-channel transimpedance amplifier EICs is ongoing. To achieve the necessary speed and low power consumption, a 28 nm CMOS process was selected. The design and layout of the Tx EIC is completed, while the design of the Rx EIC is still ongoing.
The obtained results have been covered in the previous section on main achievements.