Periodic Reporting for period 1 - FOCUSING (Full eurOpean hdi pCb and assembly sUpply chain for Space and INdustrial seGments)
Período documentado: 2022-12-01 hasta 2024-05-31
FOCUSING is a powerful playground in which outstanding, worldwide recognized European companies with complementary expertise and state-of-the-art facilities will share and merge their experience with the ultimate goal of exploring and exploiting novel, green-oriented routes towards the significant upgrading of the current printed circuit board (PCB) and surface mount technology (SMT) and the enhancement of the overall European competitiveness. Even though space market is addressed in priority, other applications may be addressed.
The growing trend towards miniaturization and the demand of ever more compact and integrated devices have led to an ever-increasing interest in printed circuit board with embedded components and in HDI boards, both for the multiple potentialities of a technical-productive nature, and for the encouraging growth prospects of the market demand.
Despite improved manufacturing HDI technologies have been widely demonstrated, and exploited e.g. for automotive, biomedical, and commercial applications, incorporating these improvements in capability with space reliability requirements still representing a challenge.
In this project, HDI technology is considered pivotal for the integration of cutting-edge electronic solutions able to revolutionize the design of present and future products (e.g. from standard sized to micro and nano satellites) by reducing the payload and boosting the performances of the space equipment.
The objective of the proposed activity is double:
• To develop and validate state-of-the-art building blocks to demonstrate the reliability of the technologies and processes developed
• To build a fully European competitive, sustainable and independent supply chain based on state-of-the-art laminates and cutting-edge HDI PCB manufacturing technology focused on advanced Space applications but potentially benefiting as well to other applications.
The main objectives are to validate European base materials and to develop and validate cutting-edge SiP complex Buildup substrate, Power embedded SiP, HDI PCB technological building blocks required for the three products to reach TRL7.
Finally, technological digital SiP and functional RF SiP demonstrators will be realized and evaluated to reach TRL 6 as well as SiP Lead-free assembly on HDI PCB mother board.
The Technical Objectives are summarized hereafter:
Techn. Obj 1 Embedding technology development & validation targeting TRL6, covering Power SiP, together with FR4 like material validation targeting TRL 7
Techn. Obj 2 Build-up structure 7-N-7 covering both, Digital SiP and RF SiP development & validation targeting TRL7
Techn. Obj 3 RF PCB HDI 3 levels of µvia development & validation up to TRL 7, covering mother boards for both Digital & RF SiP together with Megtron 6 validation targeting TRL 7
Techn. Obj 4 Equipped Technological Digital SiP validation targeting TRL 6
Techn. Obj 5 Equipped Functional RF SiP validation targeting TRL 6
Techn. Obj 6 FC- BGA SiP (RF & Digital) Lead free assembly on HDI PCB validation targeting to TRL 7
The growing trend towards miniaturization and the demand of ever more compact and integrated devices have led to an ever-increasing interest in printed circuit board with embedded components and in HDI boards, both for the multiple potentialities of a technical-productive nature, and for the encouraging growth prospects of the market demand.
Despite improved manufacturing HDI technologies have been widely demonstrated, and exploited e.g. for automotive, biomedical, and commercial applications, incorporating these improvements in capability with space reliability requirements still representing a challenge.
In this project, HDI technology is considered pivotal for the integration of cutting-edge electronic solutions able to revolutionize the design of present and future products (e.g. from standard sized to micro and nano satellites) by reducing the payload and boosting the performances of the space equipment.
The objective of the proposed activity is double:
• To develop and validate state-of-the-art building blocks to demonstrate the reliability of the technologies and processes developed
• To build a fully European competitive, sustainable and independent supply chain based on state-of-the-art laminates and cutting-edge HDI PCB manufacturing technology focused on advanced Space applications but potentially benefiting as well to other applications.
The main objectives are to validate European base materials and to develop and validate cutting-edge SiP complex Buildup substrate, Power embedded SiP, HDI PCB technological building blocks required for the three products to reach TRL7.
Finally, technological digital SiP and functional RF SiP demonstrators will be realized and evaluated to reach TRL 6 as well as SiP Lead-free assembly on HDI PCB mother board.
The Technical Objectives are summarized hereafter:
Techn. Obj 1 Embedding technology development & validation targeting TRL6, covering Power SiP, together with FR4 like material validation targeting TRL 7
Techn. Obj 2 Build-up structure 7-N-7 covering both, Digital SiP and RF SiP development & validation targeting TRL7
Techn. Obj 3 RF PCB HDI 3 levels of µvia development & validation up to TRL 7, covering mother boards for both Digital & RF SiP together with Megtron 6 validation targeting TRL 7
Techn. Obj 4 Equipped Technological Digital SiP validation targeting TRL 6
Techn. Obj 5 Equipped Functional RF SiP validation targeting TRL 6
Techn. Obj 6 FC- BGA SiP (RF & Digital) Lead free assembly on HDI PCB validation targeting to TRL 7
In the frame of Task 2100, Thales Alenia Space France has specified and designed two technological models for digital & power supply so called embedded SiP (TV1) and Digital SiP (TV2) respectively. The main activities from the last periodic report include the analyses of manufacturing & test results regarding TV1 & TV2 and the definition and follow up of corrective actions to set up for run 2. Based on previous analyses, delta design for run 2 have been realized.
All results lead to establish a corrective action plan for run#2. Actions identified are expected to improve manufacturing at the substrates level but also improve the reliability both substrate and assembly.
In the frame of Task 2200, Thales Alenia Space Italy has specified and designed two technological models TV3 and TV4. The TV3 manufacturing was conducted in two phases, called RUN 1 and RUN 1bis, due to major issues that necessitated restarting the panel manufacturing process. The first manufacturing run encountered numerous failures during the final electrical test, with open circuit conditions leading to the rejection of most pieces.
Since the low yield of TV3 RUN 1 was attributed to challenges in setting up the manufacturing process for a new material rather than design flaws, in agreement with the partners, SOMACIS decided to launch a second, unplanned run, TV3 RUN 1bis.
The RUN 1bis manufacturing process implemented all the corrections discussed previously. Despite a more refined setup, the manufacturing yield was only around 12%.
Despite the low yield, the corrections successfully reduced the warpage of the substrate without a stiffener to levels comparable to those of the TAS-F TV2. However, some substrates still exhibited localized warpage greater than 40 µm, making it difficult to mount the 150 µm pitch flip-chips, though overall output had significantly improved.
TV4 PCB was designed by TAS-I and produced by Somacis as part of the project. The test sequences, carried out by Hytek, were based on the European Space standard ECSS-Q-ST-70-60C.
The results of the tests confirm the pertinence of the proposed design. All environmental tests have been successfully carried out. In the IST on three MV configurations up to 1000 cycles, no issues were found, suggesting that these configurations can be adopted for the RUN2 and DEMO phases.
In the frame of Tasks 2100, 2200,2300, 2400,Panasonics has performed following tasks:
1) Selection and supply of the Material for the Test Vehicles and Demonstrator
2) Implementation of Appendix A confirm Material form EU production
3) Implementation plan for Megtron6 full EU production.
The resulted seleted materials for RUN1 are as follows:
- TV1 Embedding R1566S (EU)
- TV2 Digital SiP substrate Meg6 (EU) + R-G740M (Japan)
- TV3 RF SiP substrate Meg7N (Japan) + R-G740M (Japan
- TV4 Meg6 (EU)
In the frame of Tasks 2300, and 2400 SOMACIS conducted the manufacturing of RUN 1 TV 1 to TV4.
To define at the optimal design of the PCBs developed by TASF and TASI, a dense collaboration network was established between the engineers and researchers of the companies involved.
The team opted to realise 4 types of prototypes:
1. TV 1 – Embedded test vehicle by TASF;
2. TV2 – Test vehicle (7-N-7) for high speed applications by TASF;
3. TV3 - Test vehicle (7-N-7) for high speed applications by TASI;
4. TV4 – Hybrid Digital – RF HDI PCB by TASI.
In the frame of Tasks 2500, HYTEK performed, so, far, test on TV1, TV2 and TV4 Friom RUN1.
All results lead to establish a corrective action plan for run#2. Actions identified are expected to improve manufacturing at the substrates level but also improve the reliability both substrate and assembly.
In the frame of Task 2200, Thales Alenia Space Italy has specified and designed two technological models TV3 and TV4. The TV3 manufacturing was conducted in two phases, called RUN 1 and RUN 1bis, due to major issues that necessitated restarting the panel manufacturing process. The first manufacturing run encountered numerous failures during the final electrical test, with open circuit conditions leading to the rejection of most pieces.
Since the low yield of TV3 RUN 1 was attributed to challenges in setting up the manufacturing process for a new material rather than design flaws, in agreement with the partners, SOMACIS decided to launch a second, unplanned run, TV3 RUN 1bis.
The RUN 1bis manufacturing process implemented all the corrections discussed previously. Despite a more refined setup, the manufacturing yield was only around 12%.
Despite the low yield, the corrections successfully reduced the warpage of the substrate without a stiffener to levels comparable to those of the TAS-F TV2. However, some substrates still exhibited localized warpage greater than 40 µm, making it difficult to mount the 150 µm pitch flip-chips, though overall output had significantly improved.
TV4 PCB was designed by TAS-I and produced by Somacis as part of the project. The test sequences, carried out by Hytek, were based on the European Space standard ECSS-Q-ST-70-60C.
The results of the tests confirm the pertinence of the proposed design. All environmental tests have been successfully carried out. In the IST on three MV configurations up to 1000 cycles, no issues were found, suggesting that these configurations can be adopted for the RUN2 and DEMO phases.
In the frame of Tasks 2100, 2200,2300, 2400,Panasonics has performed following tasks:
1) Selection and supply of the Material for the Test Vehicles and Demonstrator
2) Implementation of Appendix A confirm Material form EU production
3) Implementation plan for Megtron6 full EU production.
The resulted seleted materials for RUN1 are as follows:
- TV1 Embedding R1566S (EU)
- TV2 Digital SiP substrate Meg6 (EU) + R-G740M (Japan)
- TV3 RF SiP substrate Meg7N (Japan) + R-G740M (Japan
- TV4 Meg6 (EU)
In the frame of Tasks 2300, and 2400 SOMACIS conducted the manufacturing of RUN 1 TV 1 to TV4.
To define at the optimal design of the PCBs developed by TASF and TASI, a dense collaboration network was established between the engineers and researchers of the companies involved.
The team opted to realise 4 types of prototypes:
1. TV 1 – Embedded test vehicle by TASF;
2. TV2 – Test vehicle (7-N-7) for high speed applications by TASF;
3. TV3 - Test vehicle (7-N-7) for high speed applications by TASI;
4. TV4 – Hybrid Digital – RF HDI PCB by TASI.
In the frame of Tasks 2500, HYTEK performed, so, far, test on TV1, TV2 and TV4 Friom RUN1.
FOCUSING project is developing a manufacturing capability in Europe with SOMACIS. In andition it has been implemented a developent of reliable build up substrate up to 7 layers per side and compatible to high speed data rate up to 56 Gbps using newly developed base material from Panasonic. PCB technological parameters technological parameters (line/space, dielectric material, Buildup layer thickness) and defined design rules in order to be compliant to SiP specificationhave been defined, and in the same time assuring both manufacturing feasibility and reliability.