Periodic Reporting for period 1 - MatEl (PZT and Graphene MATerials innovations for advanced opto-Electronic applications in AR and biosensing)
Período documentado: 2023-01-01 hasta 2024-06-30
Europe’s leading position in photonics and electronics can only be secured by adapting to the next generation of optoelectronic devices requirements: high performance, multi-functionality and cost efficiency in miniaturized footprint. These can only be achieved if novel schemes for on-chip integration emerge. Silicon nitride (Si3N4) is a promising candidate for optoelectronics applications; next to silicon photonics and indium phosphide, Si3N4 photonic integrated circuits have broad spectral coverage and low propagation losses. Still, Si3N4 itself has no active effect (except thermal tuning) and active functionality can be demonstrated either by integrating active components or active materials. The on-chip integration of III-V and II-VI semiconductors on Si3N4 is complicated and costly.
The EU-funded project “MatEl” introduces a novel, on-chip integration scheme enabling accurate and fast alignment and bonding of any type of chip package on Si3N4. MatEl will combine laser transfer (LIFT) and laser soldering processes to demonstrate next-gen applications, which will accelerate the industrial adoption of hybrid optoelectronic integrated circuits (OEICs) - offering high-performance, multi-functionality and cost efficiency in a miniaturized footprint. MatEl’s innovative solution, enhanced by the monolithic integration of advanced materials – graphene and high-quality PZT, will thus be demonstrated for two selected next-gen devices at TRL5:
• AR display featuring a 2D light source for light-field with on-chip RGB lasers and OEIC-based demultiplexer.
• Bio-photonic sensors for reliable and low-cost detection of Covid-19 featuring integrated on-chip VCSEL at 850 nm and Graphene-based photodetector.
The overall goal of MatEl will be achieved by consistently pursuing the following objectives:
Objective 1. Wafer–scale integration of high-quality and defect-free advanced materials.
Objective 2. To develop a novel Si3N4 wafer platform featuring etched pockets compatible with heterogeneous active components (III-V, II-V chips and electronic chips).
Objective 3. To introduce the first fully digital, laser-based approach for the bonding of heterogeneous active components on – chip, within predesignated etched pockets.
Objective 4. To Design and develop a generic housing for hybrid OEICs with different functionalities.
Objective 5. To demonstrate and validate at TRL5 advanced OEICs for two applications.
The EU-funded project “MatEl” introduces a novel, on-chip integration scheme enabling accurate and fast alignment and bonding of any type of chip package on Si3N4. MatEl will combine laser transfer (LIFT) and laser soldering processes to demonstrate next-gen applications, which will accelerate the industrial adoption of hybrid optoelectronic integrated circuits (OEICs) - offering high-performance, multi-functionality and cost efficiency in a miniaturized footprint. MatEl’s innovative solution, enhanced by the monolithic integration of advanced materials – graphene and high-quality PZT, will thus be demonstrated for two selected next-gen devices at TRL5:
• AR display featuring a 2D light source for light-field with on-chip RGB lasers and OEIC-based demultiplexer.
• Bio-photonic sensors for reliable and low-cost detection of Covid-19 featuring integrated on-chip VCSEL at 850 nm and Graphene-based photodetector.
The overall goal of MatEl will be achieved by consistently pursuing the following objectives:
Objective 1. Wafer–scale integration of high-quality and defect-free advanced materials.
Objective 2. To develop a novel Si3N4 wafer platform featuring etched pockets compatible with heterogeneous active components (III-V, II-V chips and electronic chips).
Objective 3. To introduce the first fully digital, laser-based approach for the bonding of heterogeneous active components on – chip, within predesignated etched pockets.
Objective 4. To Design and develop a generic housing for hybrid OEICs with different functionalities.
Objective 5. To demonstrate and validate at TRL5 advanced OEICs for two applications.
Within the current reporting period (RP1), the main achievements are:
Objective 1. Wafer-scale integration of high-quality and defect-free advanced materials
BSotA: Improved stress transfer into the integrated OEIC modulators/(de)multiplexers and ultra-sensitive Graphene PDs. The demultiplexing frequencies for the demonstrator AR chip have been defined. The GHz version will be studied and realized separately.
Objective 2. To develop a novel Si3N4 wafer platform featuring etched pockets compatible with heterogeneous active components (III-V, II-V chips and electronic chips)
BSotA: The first wafer scale Si3N4 platform hosting heterogeneous components. Currently, the Si3N4 platform’s theoretical study has been completely finished and the first generation of (test) chips incorporating this theoretical study are under fabrication and are expected to be delivered to the relevant partners at the beginning of the second reporting period.
Objective 3. To introduce the first fully digital, laser-based approach for the bonding of heterogeneous active components on-chip, within predesigned etched pockets
BSotA: Laser-based digital bonding of OEICs using one unified assembly station. Currently, in the design and engineering stage.
Objective 4. To Design and develop a generic housing for hybrid OEICs with different functionalities
BSotA: One modular package for multiple applications. Currently, in the design and engineering stage.
Objective 5. To demonstrate and validate at TRL5 advanced OEICs for two applications
BSotA: On-chip light sources and integrated demultiplexers & On-chip VCSEL and PD array. Currently, in the design and engineering stage.
Objective 1. Wafer-scale integration of high-quality and defect-free advanced materials
BSotA: Improved stress transfer into the integrated OEIC modulators/(de)multiplexers and ultra-sensitive Graphene PDs. The demultiplexing frequencies for the demonstrator AR chip have been defined. The GHz version will be studied and realized separately.
Objective 2. To develop a novel Si3N4 wafer platform featuring etched pockets compatible with heterogeneous active components (III-V, II-V chips and electronic chips)
BSotA: The first wafer scale Si3N4 platform hosting heterogeneous components. Currently, the Si3N4 platform’s theoretical study has been completely finished and the first generation of (test) chips incorporating this theoretical study are under fabrication and are expected to be delivered to the relevant partners at the beginning of the second reporting period.
Objective 3. To introduce the first fully digital, laser-based approach for the bonding of heterogeneous active components on-chip, within predesigned etched pockets
BSotA: Laser-based digital bonding of OEICs using one unified assembly station. Currently, in the design and engineering stage.
Objective 4. To Design and develop a generic housing for hybrid OEICs with different functionalities
BSotA: One modular package for multiple applications. Currently, in the design and engineering stage.
Objective 5. To demonstrate and validate at TRL5 advanced OEICs for two applications
BSotA: On-chip light sources and integrated demultiplexers & On-chip VCSEL and PD array. Currently, in the design and engineering stage.
MatEl introduces a novel, on-chip integration scheme enabling accurate and fast alignment and bonding of any type of chip package on Si3N4, demonstrated in two selected next-gen devices at TRL5:
• Augmented Reality (AR) display featuring a 2D light source for light-field with on-chip RGB lasers and OEIC-based demultiplexer, and
• Bio-photonic sensors for reliable and low-cost detection of Covid-19 featuring integrated on-chip VCSEL at 850 nm and photodetector.
The MatEl consortium has identified an exploitation plan focused on translating these advancements into commercial success, reinforcing collaborations, and enhancing EU industrial capabilities.
Exploitable Results (ERs) have been identified, such as LIFT process and Laser soldering optimisation, assembly and packaging processes of electronic and photonic integrated components, high-quality material development (monolayer graphene, PZT thin films), demonstration of the use of graphene as a photodetector on hybrid biosensor PICs, and in a light-field display technology for AR.
These operate in specific markets. The market for materials, especially graphene, is still in the R&D stage. Therefore, there are many opportunities for development. However, this means that further investment (whether private or public) is needed. The OEIC design, manufacturing and integration processes are already at a more advanced level. Hence, the MatEl project aims to improve and optimize these activities, by introducing more cost-effective processes.
For what concerns the IP landscape, MatEl partners will consider creating patents and patent applications, trademark applications, know-how, copyrights, and individual designs of IP in the foreground knowledge generated by them during the entire project. IP landscape analysis showed that, currently, there are no third-party IP which may threaten the exploitation of Matel results related to the project’s research landscape and limit the partner’s Freedom to Operate. On top of that, the patents owned by the consortium, as well as the leading roles and status of the involved partners, strongly indicate that this landscape will remain unchanged during the timeframe of MatEl.
• Augmented Reality (AR) display featuring a 2D light source for light-field with on-chip RGB lasers and OEIC-based demultiplexer, and
• Bio-photonic sensors for reliable and low-cost detection of Covid-19 featuring integrated on-chip VCSEL at 850 nm and photodetector.
The MatEl consortium has identified an exploitation plan focused on translating these advancements into commercial success, reinforcing collaborations, and enhancing EU industrial capabilities.
Exploitable Results (ERs) have been identified, such as LIFT process and Laser soldering optimisation, assembly and packaging processes of electronic and photonic integrated components, high-quality material development (monolayer graphene, PZT thin films), demonstration of the use of graphene as a photodetector on hybrid biosensor PICs, and in a light-field display technology for AR.
These operate in specific markets. The market for materials, especially graphene, is still in the R&D stage. Therefore, there are many opportunities for development. However, this means that further investment (whether private or public) is needed. The OEIC design, manufacturing and integration processes are already at a more advanced level. Hence, the MatEl project aims to improve and optimize these activities, by introducing more cost-effective processes.
For what concerns the IP landscape, MatEl partners will consider creating patents and patent applications, trademark applications, know-how, copyrights, and individual designs of IP in the foreground knowledge generated by them during the entire project. IP landscape analysis showed that, currently, there are no third-party IP which may threaten the exploitation of Matel results related to the project’s research landscape and limit the partner’s Freedom to Operate. On top of that, the patents owned by the consortium, as well as the leading roles and status of the involved partners, strongly indicate that this landscape will remain unchanged during the timeframe of MatEl.