Periodic Reporting for period 2 - TRISTAN (Together for RISc-V Technology and ApplicatioNs)
Reporting period: 2023-12-01 to 2024-11-30
Semihosting support was developed on both FPGA and Instruction Set Simulator based on ADL and it was completed.
RISC-V Semihosting was added into the NXP GDB, an IDE toolset allowing FileIO/syscall operations on an Instruction Set Simulator or on FPGA targets running RISC-V models.
The Software Team analyzed the simulator and the format of the tracing information it produces. A custom parser for the simulator trace was developed which enables programmatical extraction of information from it, e.g. stalls, instructions in each stage, executed instruction count, execution time. The existing framework for performance analysis was extended to support the new simulator trace format. The processing flow is composed of two stages, which interact via an abstraction layer. The first stage will extract tracing information from the trace input, e.g. which instructions were executed, branches taken/not taken, time spent executing, and create a representation with abstracts the details (trace type, format) from the content (traced instructions, time spent). This representation is then processed by multiple parts, which extract different statistics (program trace, execution timeline, code coverage, etc.) and display the results in a custom view.
Starting from ADL description of a RISC-V extension we generate the architectural description files used by the LLVM framework for register description, instruction encoding, instruction scheduling information, builtin support.
The implementation is extended to generate the SAIL model corresponding to the ADL description of a RISC-V extension. This feature is useful when ratifying RISCV extensions. As an example we are using the tool to generate Zilsd/Zclsd SAIL model.
This project automatically generates tests for instruction encoding, relocation tests, instruction scheduling tests using llvm-mca, and builtin tests from ADL model. This is valuable when developing support for new extensions.
RISC-V Semihosting was added into the NXP GDB, an IDE toolset allowing FileIO/syscall operations on an Instruction Set Simulator or on FPGA targets running RISC-V models.
The Software Team analyzed the simulator and the format of the tracing information it produces. A custom parser for the simulator trace was developed which enables programmatical extraction of information from it, e.g. stalls, instructions in each stage, executed instruction count, execution time. The existing framework for performance analysis was extended to support the new simulator trace format. The processing flow is composed of two stages, which interact via an abstraction layer. The first stage will extract tracing information from the trace input, e.g. which instructions were executed, branches taken/not taken, time spent executing, and create a representation with abstracts the details (trace type, format) from the content (traced instructions, time spent). This representation is then processed by multiple parts, which extract different statistics (program trace, execution timeline, code coverage, etc.) and display the results in a custom view.
Starting from ADL description of a RISC-V extension we generate the architectural description files used by the LLVM framework for register description, instruction encoding, instruction scheduling information, builtin support.
The implementation is extended to generate the SAIL model corresponding to the ADL description of a RISC-V extension. This feature is useful when ratifying RISCV extensions. As an example we are using the tool to generate Zilsd/Zclsd SAIL model.
This project automatically generates tests for instruction encoding, relocation tests, instruction scheduling tests using llvm-mca, and builtin tests from ADL model. This is valuable when developing support for new extensions.
The project started officially on the 1st December 2022. In December, the project coordinator, the work packages leaders and the country-coordinators performed detailed preparatory planning activities so that the project can start operationally in january 2023. The project's kick-off meeting is on the 11th and 12th of January in the French city of Caen, while two additional (hybrid) technical meetings have been held in Munich (Feb 2023 and October 2023).
WP1 is supporting WP2, WP3, WP4, WP5 and WP6 by providing requirements covering activities in the design and verification process of RISC-V processors, peripherals and demonstrators. A total of 38 beneficiaries are involved in the work package. The work package started as planned with M01 and has been progressing up to M06 during the RP1, after that some small iterations have been needed to complete D6.1 and D1.3. A new iteration of requirements is scheduled to start in year 2 of TRISTAN.
WP2 Processor Families Design plays a central technical role within the TRISTAN project and provides the basis for all further technical activities in this initiative. All planned tasks in WP2 could be started as planned in the project plan with M3. At least the first setup activities or initial development work could be carried out in all tasks. Joint activities between the partners could be initiated. At the task level, constructive technical meetings were organised, and concrete activities were discussed. To ensure a close collaboration within the whole consortium, interactions, and meetings with WP1, WP3 and WP6 were organized. First release of Deliverable 2.1 Initial specifications was according planning.
WP3 aims to develop high-quality hardware peripherals to support RISC-V based systems. During the first year of TRISTAN, WP3 partners generally focused on design specifications of hardware peripherals. The work package started as planned in M4 and six work package level meetings (the first one is hybrid, and the rest is virtual) have been held so far. The technical activities in this work package have generally focused on the review of the requirements, analysis of state of the art, definition of dependencies (to specify which hardware peripheral is linked to which task in which WP) and preparing the specifications for hardware peripherals.
WP4 aims on developing software for RISC-V IPs, developments have been on schedule for WP4 and connections with other WPs to collect requirements are in place. Most partners have started technical activities, with minimal structural delays due to inherent dependencies.
WP5 Tools & Methods for architectural exploration of RISC-V designs IPs and systems is progressing according planning. Tool development and enhancements have been achieved, some of which have been released in open source. Well-established collaborations, both between tool providers and users, and among providers of diverse tools. Organized several workshops focused on extra-functional property modelling, mainly performance, and high-level simulation tools and methodologies.
WP6 aims to deliver demonstrators that include IPs from other Workpackages. At YR1 . Demonstrators’ requirements and architectural mapping initial versions were provided for most demonstrators, including design specifications.
WP7 concerns project management, dissemination and training. Project Management structure has been implemented and deliverables have been submitted (Dissemination plan, Data Management Plan, Handbook etc). Many partners have contributed to TRISTAN dissemination activities, and first RISC-V training has been provided on the EU RISC-V summit in Barcelona.
WP1 is supporting WP2, WP3, WP4, WP5 and WP6 by providing requirements covering activities in the design and verification process of RISC-V processors, peripherals and demonstrators. A total of 38 beneficiaries are involved in the work package. The work package started as planned with M01 and has been progressing up to M06 during the RP1, after that some small iterations have been needed to complete D6.1 and D1.3. A new iteration of requirements is scheduled to start in year 2 of TRISTAN.
WP2 Processor Families Design plays a central technical role within the TRISTAN project and provides the basis for all further technical activities in this initiative. All planned tasks in WP2 could be started as planned in the project plan with M3. At least the first setup activities or initial development work could be carried out in all tasks. Joint activities between the partners could be initiated. At the task level, constructive technical meetings were organised, and concrete activities were discussed. To ensure a close collaboration within the whole consortium, interactions, and meetings with WP1, WP3 and WP6 were organized. First release of Deliverable 2.1 Initial specifications was according planning.
WP3 aims to develop high-quality hardware peripherals to support RISC-V based systems. During the first year of TRISTAN, WP3 partners generally focused on design specifications of hardware peripherals. The work package started as planned in M4 and six work package level meetings (the first one is hybrid, and the rest is virtual) have been held so far. The technical activities in this work package have generally focused on the review of the requirements, analysis of state of the art, definition of dependencies (to specify which hardware peripheral is linked to which task in which WP) and preparing the specifications for hardware peripherals.
WP4 aims on developing software for RISC-V IPs, developments have been on schedule for WP4 and connections with other WPs to collect requirements are in place. Most partners have started technical activities, with minimal structural delays due to inherent dependencies.
WP5 Tools & Methods for architectural exploration of RISC-V designs IPs and systems is progressing according planning. Tool development and enhancements have been achieved, some of which have been released in open source. Well-established collaborations, both between tool providers and users, and among providers of diverse tools. Organized several workshops focused on extra-functional property modelling, mainly performance, and high-level simulation tools and methodologies.
WP6 aims to deliver demonstrators that include IPs from other Workpackages. At YR1 . Demonstrators’ requirements and architectural mapping initial versions were provided for most demonstrators, including design specifications.
WP7 concerns project management, dissemination and training. Project Management structure has been implemented and deliverables have been submitted (Dissemination plan, Data Management Plan, Handbook etc). Many partners have contributed to TRISTAN dissemination activities, and first RISC-V training has been provided on the EU RISC-V summit in Barcelona.
An automated flow from the architecture description language to a SAIL model for custom instructions was achieved.