Together for RISc-V Technology and ApplicatioNs

Project Information

TRISTAN

Grant agreement ID: 101095947

DOI

10.3030/101095947

EC signature date 27 November 2022

Start date 1 December 2022

End date 30 November 2025

Funded under

• Digital, Industry and Space

Total cost

€ 53 724 230,31

EU contribution

€ 15 430 543,81

Coordinated by

NXP SEMICONDUCTORS GERMANY GMBH
Germany

CORDIS provides links to public deliverables and publications of HORIZON projects.

Links to deliverables and publications from FP7 projects, as well as links to some specific result types such as dataset and software, are dynamically retrieved from OpenAIRE .

Deliverables

Documents, reports (7)

Design Specifications of demonstrators
Stakeholder Engagement Plan

Stakeholder Engagement Plan.

Initial requirements architectural map of the demonstrators

Initial requirements architectural map of the demonstrators.

Preliminary integration Report
Intermediate requirements architectural map of the demonstrators
Initial requirements and feedback for SW and EDA Tools IPs

Initial requirements and feedback for SW and EDA Tools IPs.

Initial requirements and feedback for processor and hardware IPs

Development of initial requirements and feedback for processor and hardware IPs.

Data sets, microdata, etc (1)

Intermediate virtual repository and coupling to OpenHWG repository created

Intermediate virtual repository and coupling to OpenHWG repository created.

Other (2)

EDA framework for RISC-V - prototype, report, Open-Source
All governance boards installed

All governance boards installed.

Publications

Conference proceedings (13)

SeTHet - Sending Tuned numbers over DMA onto Heterogeneous clusters: an automated precision tuning story

Author(s): Gabriele Magnani, Daniele Cattaneo, Lev Denisov, Giuseppe Tagliavini, Giovanni Agosta, Stefano Cherubin
Published in: Proceedings of the 21st ACM International Conference on Computing Frontiers, 2024
Publisher: ACM
DOI: 10.1145/3649153.3649203

Trikarenos: A Fault-Tolerant RISC-V-based Microcontroller for CubeSats in 28nm

Author(s): Michael Rogenmoser, Luca Benini
Published in: 2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2024
Publisher: IEEE
DOI: 10.1109/ICECS58634.2023.10382727

Implementation and integration of Keccak accelerator on RISC-V for CRYSTALS-Kyber

Author(s): Alessandra Dolmeta, Mattia Mirigaldi, Maurizio Martina, and Guido Masera
Published in: Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023
Publisher: ACM
DOI: 10.1145/3587135.3591432

Hardware architecture for CRYSTALS-Kyber post-quantum cryptographic SHA-3 primitives

Author(s): Dolmeta, Alessandra; Martina, Maurizio; Masera, Guido
Published in: 2023 18th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), 2023
Publisher: IEEE
DOI: 10.1109/prime58259.2023.10161780

AXI-REALM: A Lightweight and Modular Interconnect Extension for Traffic Regulation and Monitoring of Heterogeneous Real-Time SoCs

Author(s): Thomas Benz, Alessandro Ottaviano, Robert Balas, Angelo Garofalo, Francesco Restuccia, Alessandro Biondi, Luca Benini
Published in: 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2024
Publisher: IEEE
DOI: 10.23919/DATE58400.2024.10546511

Lightweight Instrumentation for Accurate Performance Monitoring in RTOSes

Author(s): Bruno Forlin, Kuan-Hsun Chen, Nikolaos Alachiotis, Luca Cassano, Marco Ottavi
Published in: 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2024
Publisher: IEEE
DOI: 10.23919/DATE58400.2024.10546790

An unprotected RISC-V Soft-core processor on an SRAM FPGA: Is it as bad as it sounds?

Author(s): Bruno Endres Forlin, Wouter van Huffelen, Carlo Cazzaniga, Paolo Rech, Nikolaos Alachiotis, Marco Ottavi
Published in: 2023 IEEE European Test Symposium (ETS), 2023
Publisher: IEEE
DOI: 10.1109/ETS56758.2023.10174076

Neutron Radiation Tests of the NEORV32 RISC-V SoC on Flash-Based FPGAs

Author(s): Kevin Böhmer, Bruno Forlin, Carlo Cazzaniga, Paolo Rech, Gianluca Furano, Nikolaos Alachiotis, Marco Ottavi
Published in: 2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2024
Publisher: IEEE
DOI: 10.1109/DFT59622.2023.10313556

Preventing Soft Errors and Hardware Trojans in RISC-V Cores

Author(s): Edian B. Annink, Gerard Rauwerda, Edwin Hakkennes, Alessandra Menicucci, Stefano Di Mascio, Gianluca Furano, Marco Ottavi
Published in: 2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2022
Publisher: IEEE
DOI: 10.1109/DFT56152.2022.9962340

PLiNIO: A User-Friendly Library of Gradient-Based Methods for Complexity-Aware DNN Optimization

Author(s): D. Jahier Pagliari, M. Risso, B. A. Motetti and A. Burrello
Published in: 2023 Forum on Specification & Design Languages (FDL), 2023, ISSN 1636-9874
Publisher: IEEE
DOI: 10.1109/FDL59689.2023.10272045

HPDcache

Author(s): César Fuguet
Published in: Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023, ISSN 1942-3462
Publisher: ACM
DOI: 10.1145/3587135.3591413

Neutron Beam Evaluation of Probabilistic Data Structure-based Online Checkers

Author(s): Bruno Forlin, Edian B. Annink, Elijah Cishugi, Carlo Cazzaniga, Paolo Rech, Gerard Rauwerda, Gianluca Furano, Marco Ottavi
Published in: 2024 IEEE 30th International Symposium on On-Line Testing and Robust System Design (IOLTS), 2024
Publisher: IEEE
DOI: 10.1109/IOLTS60994.2024.10616084

An Enhanced Fault Injection Framework for FPGA-Based Soft-Cores

Author(s): Tijmen T. Smit, Bruno Endres Forlin, Kuan-Hsun Chen, Ioanna Souvatzoglou, Mihalis Psarakis, Marco Ottavi
Published in: 2024 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2024
Publisher: IEEE
DOI: 10.1109/DFT63277.2024.10753564

Peer reviewed articles (8)

Hybrid Modular Redundancy: Exploring Modular Redundancy Approaches in RISC-V Multi-Core Computing Clusters for Reliable Processing in Space

Author(s): Michael Rogenmoser; Yvan Tortorella; Davide Rossi; Francesco Conti; Luca Benini
Published in: ACM Transactions on Cyber-Physical Systems, 2023, ISSN 2378-9638
Publisher: Association for Computing Machinery
DOI: 10.48550/arxiv.2303.08706

Energy-Efficient Exposed Datapath Architecture With a RISC-V Instruction Set Mode

Author(s): Kari Hepola, Joonas Multanen, Pekka Jääskeläinen
Published in: IEEE Transactions on Computers, Issue 73, 2024, ISSN 0018-9340
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
DOI: 10.1109/TC.2023.3337313

Enhancing Neural Architecture Search with Multiple Hardware Constraints for Deep Learning Model Deployment on Tiny IoT Devices

Author(s): A. Burrello, M. Risso, B. A. Motetti, E. Macii, L. Benini and D. J. Pagliari,
Published in: IEEE Transactions on Emerging Topics in Computing, 2023, ISSN 2168-6750
Publisher: IEEE
DOI: 10.1109/TETC.2023.3322033

MARLIN: A Co-Design Methodology for Approximate ReconfigurabLe Inference of Neural Networks at the Edge

Author(s): Guella, Flavia; Valpreda, Emanuele; Caon, Michele; Masera, Guido; Martina, Maurizio
Published in: IEEE Transactions on Circuits and Systems I: Regular Papers, 2024, ISSN 1558-0806
Publisher: IEEE
DOI: 10.1109/tcsi.2024.3365952

A 3 TOPS/W RISC-V Parallel Cluster for Inference of Fine-Grain Mixed-Precision Quantized Neural Networks

Author(s): Nadalini, A; Rutishauser, G; Burrello, A; Bruschi, N; Garofalo, A; Benini, L; Conti, F; Rossi, D
Published in: 2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2023, ISSN 2159-3477
Publisher: IEEE
DOI: 10.48550/arxiv.2307.01056

Keelhaul: Processor-Driven Chip Connectivity and Memory Map Metadata Validator for Large Systems-on-Chip

Author(s): Henri Lunnikivi, Roni Hämäläinen, Timo D. Hämäläinen
Published in: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Issue 32, 2024, ISSN 1063-8210
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
DOI: 10.1109/TVLSI.2024.3454431

ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation

Author(s): Ottaviano, Alessandro; Balas, Robert; Bambini, Giovanni; Del Vecchio, Antonio; Ciani, Maicol; Rossi, Davide; Benini, Luca; Bartolini, Andrea
Published in: International Journal of Parallel Programming, 2023, ISSN 1573-7640
Publisher: nternational Journal of Parallel Programming
DOI: 10.21203/rs.3.rs-2525734/v1

<i>Xvpfloat</i>: RISC-V ISA Extension for Variable Extended Precision Floating Point Computation

Author(s): Eric Guthmuller; César Fuguet; Andrea Bocco; Jérôme Fereyre; Riccardo Alidori; Ihsane Tahir; Yves Durand
Published in: IEEE Transactions on Computers, 2024, ISSN 1557-9956
Publisher: IEEE
DOI: 10.1109/tc.2024.3383964

Other (2)

Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC With 2–8 b DNN Acceleration and 30%-Boost Adaptive Body Biasing

Author(s): Francesco Conti; Gianna Paulin; Angelo Garofalo; Davide Rossi; Alfio Di Mauro; Georg Rutishauser; Gianmarco Ottavi; Manuel Eggiman; Hayate Okuhara; Luca Benini
Published in: IEEE Journal of Solid-State Circuits, 2024, ISSN 1558-173X
Publisher: IEEE
DOI: 10.48550/arxiv.2305.08415

Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-In

Author(s): Alessandro Ottaviano; Thomas Benz; Paul Scheffler; Luca Benini
Published in: IEEE Transactions on Circuits and Systems II: Express Briefs, 2023, ISSN 1558-3791
Publisher: IEEE
DOI: 10.3929/ethz-b-000638551