Periodic Reporting for period 1 - TRISTAN (Together for RISc-V Technology and ApplicatioNs)
Berichtszeitraum: 2022-12-01 bis 2023-11-30
The EC Chips Act considers the creation and expansion of a RISC-V Open-Source ecosystem to be a strategic investment that will enable Europe to reach the ambitions of doubling the value of design and production of semiconductors in Europe by 2030. Thus far, however, there has been no widely accepted Open-Source alternative for the hardware that underpins Open-Source. In fact, CPU, GPU and ASIC (Application Specific Integrated Circuits) development is still mostly proprietary with very few – mainly US-based – players. These players are meeting the exponential increase in demand for computational performance, but the associated development costs– for design, and verification before sign-off –becomes less and less sustainable. In this international context, European companies are in a subordinate position: currently they have to either buy processors designed and manufactured outside Europe, or they have to rely on non-European IP providers for their processor chip designs. In contrast, Open-Source RISC-V with Instruction Extensions based cloud computing is expected to be significantly more energy- and cost-efficient for Artificial Intelligence (AI) and Machine Learning (ML) based workloads and stimulate innovation opportunities a more open approach to processor design. Hence we see a RISC-V and open hardware as a major opportunity for Europe to leverage on the High Performance Computing (HPC), automotive, communication and industrial expertise that has been built up over the years and push it from application to hardware. There is now room for European companies to expand the current microelectronic focus areas towards compute-intensive applications.
The TRISTAN project's overarching aim is to expand, mature and industrialize the European RISC-V ecosystem so that it is able to compete with existing commercial/proprietary alternatives. This will be achieved by leveraging the Open-Source community to gain in productivity and quality. This goal will be achieved by defining a European strategy for RISC-V based designs including the creation of a repository of industrial quality building blocks to be used for SoC designs in different application domains (e.g. automotive, industrial, etc.). The TRISTAN approach is holistic, covering both electronic design automation tools (EDA) and the full software stack. The broad consortium will expose a large number of engineers to RISC-V technology, which will further strengthen adoption. This ecosystem will ensure a European sovereign alternative to existing commercial/proprietary players. The focus of the consortium is to ensure the building blocks become easily available to industrial users. Given this focus, TRISTAN has established the following focus areas:
• Thorough and consistent test plans and verification suites for 100% coverage.
• Complete and accurate documentation.
• Rich variety of fully functional supporting building blocks.
• Fully functional, fast and efficient, RISC-V related Open-Source EDA tools.
• Supporting software libraries and support tooling.
• Permissive licencing terms.
The TRISTAN project's overarching aim is to expand, mature and industrialize the European RISC-V ecosystem so that it is able to compete with existing commercial/proprietary alternatives. This will be achieved by leveraging the Open-Source community to gain in productivity and quality. This goal will be achieved by defining a European strategy for RISC-V based designs including the creation of a repository of industrial quality building blocks to be used for SoC designs in different application domains (e.g. automotive, industrial, etc.). The TRISTAN approach is holistic, covering both electronic design automation tools (EDA) and the full software stack. The broad consortium will expose a large number of engineers to RISC-V technology, which will further strengthen adoption. This ecosystem will ensure a European sovereign alternative to existing commercial/proprietary players. The focus of the consortium is to ensure the building blocks become easily available to industrial users. Given this focus, TRISTAN has established the following focus areas:
• Thorough and consistent test plans and verification suites for 100% coverage.
• Complete and accurate documentation.
• Rich variety of fully functional supporting building blocks.
• Fully functional, fast and efficient, RISC-V related Open-Source EDA tools.
• Supporting software libraries and support tooling.
• Permissive licencing terms.
The project started officially on the 1st December 2022. In December, the project coordinator, the work packages leaders and the country-coordinators performed detailed preparatory planning activities so that the project can start operationally in january 2023. The project's kick-off meeting is on the 11th and 12th of January in the French city of Caen, while two additional (hybrid) technical meetings have been held in Munich (Feb 2023 and October 2023).
WP1 is supporting WP2, WP3, WP4, WP5 and WP6 by providing requirements covering activities in the design and verification process of RISC-V processors, peripherals and demonstrators. A total of 38 beneficiaries are involved in the work package. The work package started as planned with M01 and has been progressing up to M06 during the RP1, after that some small iterations have been needed to complete D6.1 and D1.3. A new iteration of requirements is scheduled to start in year 2 of TRISTAN.
WP2 Processor Families Design plays a central technical role within the TRISTAN project and provides the basis for all further technical activities in this initiative. All planned tasks in WP2 could be started as planned in the project plan with M3. At least the first setup activities or initial development work could be carried out in all tasks. Joint activities between the partners could be initiated. At the task level, constructive technical meetings were organised, and concrete activities were discussed. To ensure a close collaboration within the whole consortium, interactions, and meetings with WP1, WP3 and WP6 were organized. First release of Deliverable 2.1 Initial specifications was according planning.
WP3 aims to develop high-quality hardware peripherals to support RISC-V based systems. During the first year of TRISTAN, WP3 partners generally focused on design specifications of hardware peripherals. The work package started as planned in M4 and six work package level meetings (the first one is hybrid, and the rest is virtual) have been held so far. The technical activities in this work package have generally focused on the review of the requirements, analysis of state of the art, definition of dependencies (to specify which hardware peripheral is linked to which task in which WP) and preparing the specifications for hardware peripherals.
WP4 aims on developing software for RISC-V IPs, developments have been on schedule for WP4 and connections with other WPs to collect requirements are in place. Most partners have started technical activities, with minimal structural delays due to inherent dependencies.
WP5 Tools & Methods for architectural exploration of RISC-V designs IPs and systems is progressing according planning. Tool development and enhancements have been achieved, some of which have been released in open source. Well-established collaborations, both between tool providers and users, and among providers of diverse tools. Organized several workshops focused on extra-functional property modelling, mainly performance, and high-level simulation tools and methodologies.
WP6 aims to deliver demonstrators that include IPs from other Workpackages. At YR1 . Demonstrators’ requirements and architectural mapping initial versions were provided for most demonstrators, including design specifications.
WP7 concerns project management, dissemination and training. Project Management structure has been implemented and deliverables have been submitted (Dissemination plan, Data Management Plan, Handbook etc). Many partners have contributed to TRISTAN dissemination activities, and first RISC-V training has been provided on the EU RISC-V summit in Barcelona.
WP1 is supporting WP2, WP3, WP4, WP5 and WP6 by providing requirements covering activities in the design and verification process of RISC-V processors, peripherals and demonstrators. A total of 38 beneficiaries are involved in the work package. The work package started as planned with M01 and has been progressing up to M06 during the RP1, after that some small iterations have been needed to complete D6.1 and D1.3. A new iteration of requirements is scheduled to start in year 2 of TRISTAN.
WP2 Processor Families Design plays a central technical role within the TRISTAN project and provides the basis for all further technical activities in this initiative. All planned tasks in WP2 could be started as planned in the project plan with M3. At least the first setup activities or initial development work could be carried out in all tasks. Joint activities between the partners could be initiated. At the task level, constructive technical meetings were organised, and concrete activities were discussed. To ensure a close collaboration within the whole consortium, interactions, and meetings with WP1, WP3 and WP6 were organized. First release of Deliverable 2.1 Initial specifications was according planning.
WP3 aims to develop high-quality hardware peripherals to support RISC-V based systems. During the first year of TRISTAN, WP3 partners generally focused on design specifications of hardware peripherals. The work package started as planned in M4 and six work package level meetings (the first one is hybrid, and the rest is virtual) have been held so far. The technical activities in this work package have generally focused on the review of the requirements, analysis of state of the art, definition of dependencies (to specify which hardware peripheral is linked to which task in which WP) and preparing the specifications for hardware peripherals.
WP4 aims on developing software for RISC-V IPs, developments have been on schedule for WP4 and connections with other WPs to collect requirements are in place. Most partners have started technical activities, with minimal structural delays due to inherent dependencies.
WP5 Tools & Methods for architectural exploration of RISC-V designs IPs and systems is progressing according planning. Tool development and enhancements have been achieved, some of which have been released in open source. Well-established collaborations, both between tool providers and users, and among providers of diverse tools. Organized several workshops focused on extra-functional property modelling, mainly performance, and high-level simulation tools and methodologies.
WP6 aims to deliver demonstrators that include IPs from other Workpackages. At YR1 . Demonstrators’ requirements and architectural mapping initial versions were provided for most demonstrators, including design specifications.
WP7 concerns project management, dissemination and training. Project Management structure has been implemented and deliverables have been submitted (Dissemination plan, Data Management Plan, Handbook etc). Many partners have contributed to TRISTAN dissemination activities, and first RISC-V training has been provided on the EU RISC-V summit in Barcelona.