Dirac cold-source transistor technologies towards attojoule switching

Project Information

AttoSwitch

Grant agreement ID: 101135571

DOI

10.3030/101135571

EC signature date 30 November 2023

Start date 1 January 2024

End date 30 June 2027

Funded under

• Digital, Industry and Space

Total cost

€ 3 884 248,75

EU contribution

€ 3 884 248,50

Coordinated by

CONSORZIO NAZIONALE INTERUNIVERSITARIO PER LA NANOELETTRONICA
Italy

Periodic Reporting for period 1 - AttoSwitch (Dirac cold-source transistor technologies towards attojoule switching)

Reporting period: 2024-01-01 to 2025-06-30

Summary of the context and overall objectives of the project

Global energy demand for information and communication technologies may reach up to 20% of total energy by the end of the decade. Innovations on transistor technologies, following Moore’s law, can in part compensate for this rise and improve sustainability by providing more energy-efficient electronics. However, the energy-efficiency of CMOS is limited by the Boltzmann physics, which sets a lower bound on the operating voltage, and thereby the power. To sustain miniaturization, and improved performance of electronics, new transistor technologies are needed that can overcome this limit.
AttoSwitch, started in January 2024, aims to develop a novel cold-source transistor technology that uses the intrinsically cold carrier distribution of Dirac semimetals to overcome the Boltzmann limit and achieve an ultra low switching energy of a few attojoules. The main objective is to develop a scalable Dirac transistor (DFET) technology based on large area integration of 2D and 3D Dirac materials, e.g. graphene and CoSi, and the realization of high-performance device demonstrators at technologically relevant length scales. Key demonstrators are based on graphene integrated with MoS2 channels, as well as novel work on 3D Dirac semimetals for integration of cold-source in advanced transistor technologies.
Our methodology includes development of device process modules and extensive material and device characterization. Systematic modeling using new simulation frameworks for DFETs at different levels of abstraction, plays a key part to steer material selection, support optimized design of DFET architectures, interpret experiments, accurately predict performance, assess technology maturity, benchmark and provide a road map for the technology.

Work performed from the beginning of the project to the end of the period covered by the report and main results achieved so far

The first one and a half years of the AttoSwitch project has been defined by notable accomplishments in all scientific and management work packages. The project's kick-off meeting (Modena, Italy, February 2024) laid a solid foundation for systematic, effective, and productive collaboration among partners. Initial delays with the hiring procedures have been eventually overcome and the project is now running at full pace in all WPs.
Advanced modelling and simulation frameworks for DFETs and contacts have been developed at different levels of abstraction (from atomistic ab-initio to TCAD and semi-analytical), supporting the project with a portfolio of simulation tools, providing remarkable insights on expected material performance, suggesting new or optimized device structures, enabling to pinpoint some of the fundamental physical limitations.
First versions of processes to deposit/grow, etch, and integrate 2D and 3D Dirac materials with semiconductors have been developed. Processing windows to limit the detrimental effects of PMMA residues, layer delamination, and cleaning procedures have been tested, eventually leading to the successful fabrication of: 1) prototypical Dirac junctions of 2D and 3D Dirac materials with semiconductors; 2) functional transistors with Graphene/MoS2. These devices are currently under scrutiny to identify the limiting factors toward the observation of sub-thermal subthreshold swing. Fabrication of more complex demonstrators with scaled gate dielectric is ongoing.
Advanced TEM/STEM characterizations have provided a wealth of morphological, compositional, structural, and electrostatic information on the newly fabricated 2D and 3D Dirac material samples, thanks to an intense and fruitful collaboration among partners. Valuable insights have been achieved to understand the effectiveness of the processing steps in providing high quality graphene and MoS2 layers, and CoSn crystals. Defect analysis has started and will be further pursued in the future.
Several peer-reviewed journal and conference papers have been published. A very successful inter-EU-project workshop has been organized in Aachen to foster dissemination, networking, and collaboration at European level.

Progress beyond the state of the art and expected potential impact (including the socio-economic impact and the wider societal implications of the project so far)

New processing steps have been tested for large scale fabrication of DFETs with high yield. Prototype junctions of 2D and 3D Dirac materials with 2D and 3D semiconductors have been demonstrated.
Ab-initio quantum transport simulations have shown that Dirac FETs with overlapped and edge-to-edge Graphene/MoS2 junctions and other material combinations can achieve steep slope operation in both nMOS and pMOS.
Electron decoherence due to phonon scattering has been identified as a major limiting factor toward subthermal swing and with the desired performance targets. Design windows to mitigate this effect have been identified for different combinations of materials.