Scalable Hardware for Large-Scale Quantum Computing

Project Information

SCALLOP

Grant agreement ID: 101136793

DOI

10.3030/101136793

EC signature date 7 September 2023

Start date 1 September 2023

End date 31 August 2026

Funded under

• The European Innovation Council (EIC)

Total cost

€ 2 499 998,75

EU contribution

€ 2 499 998,75

Coordinated by

SEMIQON TECHNOLOGIES OY
Finland

Periodic Reporting for period 1 - SCALLOP (Scalable Hardware for Large-Scale Quantum Computing)

Reporting period: 2023-09-01 to 2024-08-31

Summary of the context and overall objectives of the project

Computational power is a critical driver of innovation. The ability to quickly and accurately process large amounts of data and solve complex problems has enabled new breakthroughs in fields ranging from finance and healthcare to material science and engineering. However, traditional computing paradigms are reaching their limits. The limitations of classical computing can be overcome by quantum computing. Quantum computers excel at optimization tasks such as solving complex logistical problems; one day, they may be able to accurately model viruses and drugs, as well as come up with climate solutions .

To realize this potential, large-scale and fault-tolerant quantum computers with millions of qubits are required, which is currently not possible due to hardware and scalability limitations of currently available solutions. We overcome these challenges by incorporating a commercial-ready, scalable silicon technology for quantum processing units, where integrated cryo-CMOS multiplexer is utilized for efficient and precise control of high-quality silicon spin qubits, paving the way to accommodate millions of qubits.

The final demonstrator system built in the SCALLOP project will be a significant step forward in the development of microsystems for implementing silicon spin qubits, as well as progress toward a scalable, fault-tolerant quantum computer requiring millions of qubits.

Work performed from the beginning of the project to the end of the period covered by the report and main results achieved so far

During the first phase of the SCALLOP project we predominantly took the following actions and completed the following tasks:
- Outlined the specifications of the full-stack demonstrator
- Designed the fabrication process step for manufacturing the quantum chips.
- Completed the first fabrication run of the chips and characterization both at room and cryogenic temperatures
- Learnings from the first fabrication run was incorporated in the second fabrication run which is currently ongoing.
- Design for the final, integrated chip that is to be incorporated with the readout electronics is currently being developed.

Progress beyond the state of the art and expected potential impact (including the socio-economic impact and the wider societal implications of the project so far)

As part of the project we developed a cryogenic CMOS transistor technology that showed beyond state of the art performance. The efficient switching characteristics of this new CMOS technology enable ultra-low power cryogenic CMOS for control and interfacing of quantum processors and other quantum systems (https://arxiv.org/pdf/2410.01077).