In course of the VIVID project implementation, a prototype demonstrator system available as lab setup has been brought into operation and is available for benchmarking of application kernels and demonstrations on videantis premises.
After successful initial bring-up, initial neural network applications have successfully been mapped onto the videantis cores on the prototype chip. This way, also the correct operation of the prototype chips could be further validated. Further, a re-design of the prototype chip demonstrator in M.2 2280 format has been completed to turn the non-portable multi-board lab setup into a highly compact, portable demonstration and evaluation system. The videantis NN mapping toolflow has been expanded from single-cluster mapping mode to multi-cluster configuration support. With this expanded toolflow, a thorough architectural exploration for the overall VIVID SoC multi-cluster architecture has been performed. Based on these results, the final multi-cluster configuration to be implemented for VIVID has been determined. The overall VIVID SoC architecture has been specified, and the detailed subsystem components have been selected. The RTL code of the internal components developed has been developed, and design synthesis has been performed. Design verification through RTL simulation and FPGA mapping is ongoing. A selection of reference SW kernels from different application domains has been implemented and used for the refinement of the overall subsystem architecture. These kernels are used for the ongoing design verification including FPGA prototyping, RTL simulations, and gate-level simulations prior to sign-off. The programming tool chain has been adapted to the new architecture and will be used throughout the further process of chip design, implementation, and validation before tape-out as well as for further SW implementations on the prototyping chip in the scope of the demonstration and evaluation system.
