Periodic Reporting for period 1 - VIVID (Europe’s first unified and versatile processing platform architecture in 5nm technology with proven scalability from edge to central high-performance solutions with unmatched cost and power efficiency)
Période du rapport: 2023-12-01 au 2024-11-30
The recent chip shortage had a serious impact on many key industries and highlighted Europe's dependence on supplies from Asia and the United States and its lack of control over strategic technologies. Therefore, European industry is looking for a solution that gives it a better supply chain control, meeting the goals of the European Chips Act. In this context, the EIC-Accelerator funded VIVID project introduces a disruptive innovation which can help ensure the future strategic autonomy of the Union in the field of processor architecture design and semiconductor chips in advanced technology nodes for artificial intelligence and autonomous driving. The key technical innovation lies in the chip design performed in the highly advanced 5nm technology node based on videantis’ unique, highly scalable processor architecture, thereby addressing the stage of highest value added, and increasing European competencies in a domain which is currently mostly dominated by US and Asian companies.
VIVID will create a unified, 100 % programmable processing platform boasting superior performance, power efficiency and compactness. Processor architecture developed by videantis of Hannover, Germany, is already in use in over 20 million cars to date. Scaling up the architecture to incorporate hundreds of cores on a single 5 nm die, it serves as a reference chip platform for applications ranging from smart sensors to central high-performance computing systems for advanced driver assistance systems and autonomous driving. This diminishes Europe’s dependence on chip suppliers from China and the United States and enables European OEMs to realise own highest-performance and custom AI SoCs, potentially reducing costs by up to 90 %.
This project can therefore be the key to achieving the objectives of the EU Chips Act by bolstering Europe’s competitiveness and resilience in semiconductor technologies and applications and helping to achieve both the digital and green transitions.
VIVID will create a unified, 100 % programmable processing platform boasting superior performance, power efficiency and compactness. Processor architecture developed by videantis of Hannover, Germany, is already in use in over 20 million cars to date. Scaling up the architecture to incorporate hundreds of cores on a single 5 nm die, it serves as a reference chip platform for applications ranging from smart sensors to central high-performance computing systems for advanced driver assistance systems and autonomous driving. This diminishes Europe’s dependence on chip suppliers from China and the United States and enables European OEMs to realise own highest-performance and custom AI SoCs, potentially reducing costs by up to 90 %.
This project can therefore be the key to achieving the objectives of the EU Chips Act by bolstering Europe’s competitiveness and resilience in semiconductor technologies and applications and helping to achieve both the digital and green transitions.
In course of the VIVID project implementation, a prototype demonstrator system available as lab setup has been brought into operation and is available for benchmarking of application kernels and demonstrations on videantis premises.
After successful initial bring-up initial neural network applications have successfully been mapped onto the videantis cores on the prototype chip. This way, also the correct operation of the prototype chips could be further validated. Further, a re-design of the prototype chip demonstrator in M.2 2280 format has been completed to turn the non-portable multi-board lab setup into a highly compact, portable demonstration and evaluation system. The videantis NN mapping toolflow has been expanded from single-cluster mapping mode to multi-cluster configuration support. With this expanded toolflow, a thorough architectural exploration for the overall VIVID SoC multi-cluster architecture has been performed. Based on these results, the final multi-cluster configuration to be implemented for VIVID has been determined. The overall VIVID SoC architecture has been specified, and the detailed subsystem components have been selected. The RTL code of the internal components developed has been developed, and design synthesis has been performed. Design verification through RTL simulation and FPGA mapping is ongoing. A selection of reference SW kernels from different application domains has been implemented and used for the refinement of the overall subsystem architecture. These kernels are used for the ongoing design verification including FPGA prototyping, RTL simulations, and gate-level simulations prior to sign-off. The programming tool chain has been adapted to the new architecture and will be used throughout the further process of chip design, implementation, and validation before tape-out as well as for further SW implementations on the prototyping chip in the scope of the demonstration and evaluation system.
After successful initial bring-up initial neural network applications have successfully been mapped onto the videantis cores on the prototype chip. This way, also the correct operation of the prototype chips could be further validated. Further, a re-design of the prototype chip demonstrator in M.2 2280 format has been completed to turn the non-portable multi-board lab setup into a highly compact, portable demonstration and evaluation system. The videantis NN mapping toolflow has been expanded from single-cluster mapping mode to multi-cluster configuration support. With this expanded toolflow, a thorough architectural exploration for the overall VIVID SoC multi-cluster architecture has been performed. Based on these results, the final multi-cluster configuration to be implemented for VIVID has been determined. The overall VIVID SoC architecture has been specified, and the detailed subsystem components have been selected. The RTL code of the internal components developed has been developed, and design synthesis has been performed. Design verification through RTL simulation and FPGA mapping is ongoing. A selection of reference SW kernels from different application domains has been implemented and used for the refinement of the overall subsystem architecture. These kernels are used for the ongoing design verification including FPGA prototyping, RTL simulations, and gate-level simulations prior to sign-off. The programming tool chain has been adapted to the new architecture and will be used throughout the further process of chip design, implementation, and validation before tape-out as well as for further SW implementations on the prototyping chip in the scope of the demonstration and evaluation system.
The videantis processor architecture and related custom AI SoC offering in 5nm technology exceeds the state-of-the-art by providing a truly unified processing platform equally optimized for all relevant algorithms for ADAS and AD not found in any other existing solution. This unified processor architecture platform, incrementally perfected by videantis over 20 years, results in a much simplified SoC architecture addressing high-performance applications compared to other existing solutions, provides a seamless scalability of number of cores as well as highly reduces software complexity compared to other solutions known in the market.
Already the predecessor architecture generation of videantis has been recognized by automotive customers to provide PPA KPIs clearly exceeding other existing solutions, being the only solution on the market enabling truly single-box smart automotive cameras, which are now in serial production in millions of units.
With the latest processor architecture generation and the integration of AI processing into the same data path, the PPA lead in relation to the highly versatile scope of applications supported on the same processor architecture could even be increased further.
By offering a unique business model providing a path for European OEMs and Tier 1s to develop their own, customized AI SoC based on a proven and superior processor architecture in most advanced 5nm technology, VIVID also exceed the state-of-the-art on the business side, enabling autonomy and sovereignty to the European industry in the field of chip design and semiconductor supply.
Already the predecessor architecture generation of videantis has been recognized by automotive customers to provide PPA KPIs clearly exceeding other existing solutions, being the only solution on the market enabling truly single-box smart automotive cameras, which are now in serial production in millions of units.
With the latest processor architecture generation and the integration of AI processing into the same data path, the PPA lead in relation to the highly versatile scope of applications supported on the same processor architecture could even be increased further.
By offering a unique business model providing a path for European OEMs and Tier 1s to develop their own, customized AI SoC based on a proven and superior processor architecture in most advanced 5nm technology, VIVID also exceed the state-of-the-art on the business side, enabling autonomy and sovereignty to the European industry in the field of chip design and semiconductor supply.