Mechanical Impact on Non-silicon Devices: Stress Effects on Technology

Project Information

MINDSET

Grant agreement ID: 101154357

DOI

10.3030/101154357

Project closed

EC signature date 10 April 2024

Start date 1 August 2024

End date 31 July 2026

Funded under

• Marie Skłodowska-Curie Actions (MSCA)

Total cost

No data

EU contribution

€ 175 920,00

Coordinated by

INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM
Belgium

Periodic Reporting for period 1 - MINDSET (Mechanical Impact on Non-silicon Devices: Stress Effects on Technology)

Reporting period: 2024-08-01 to 2026-07-31

Summary of the context and overall objectives of the project

MINDSET addressed a reliability challenge for future semiconductor technologies: how local mechanical stress affects emerging non-silicon transistors when it acts alone or together with electrical and thermal stress. This is increasingly important for back-end-of-line-compatible devices, monolithic three-dimensional integration and advanced packaging, where fabrication, integration and local heating can generate stress close to active devices. The project focused on oxide-semiconductor IGZO thin-film transistors and two-dimensional WS2 field-effect transistors. Its objective was to establish an experimental and modelling pathway that links controlled local loading to changes in threshold voltage, leakage, mobility and bias-temperature instability. By enabling stress-aware reliability assessment, the project supports the development of more dependable next-generation electronic devices and strengthens European expertise in semiconductor research and advanced manufacturing.

Work performed from the beginning of the project to the end of the period covered by the report and main results achieved so far

The project established a reproducible nanoindenter-based in-situ electrical characterization workflow. Local mechanical loading was synchronized with electrical measurements, and finite-element modelling was used to convert applied force into device-level stress distributions. Systematic experiments were performed on 300 mm wafer-fabricated IGZO and WS2 devices during loading and unloading. The work compared mechanical-stress-only, electrical-stress-only and combined mechanical-plus-electrical-stress conditions, and evaluated threshold-voltage shift, subthreshold behaviour, on-current, leakage, positive-bias-temperature-instability degradation and recovery. A local Pt microheater was also integrated with IGZO test structures, enabling localized thermal control and combined electro-thermo-mechanical experiments. The experimental results were interpreted using FEM, density-functional-theory-supported analysis for IGZO, and TCAD-assisted analysis for WS2. The project produced first-author peer-reviewed publications, conference presentations, internal technical dissemination and knowledge transfer through training on the nanoindenter methodology.

Progress beyond the state of the art and expected potential impact (including the socio-economic impact and the wider societal implications of the project so far)

MINDSET advanced beyond the state of the art by demonstrating a combined experimental and simulation framework for localized GPa-level stress in emerging semiconductor devices. In IGZO TFTs, compressive mechanical stress produced a positive threshold-voltage shift of about 100 mV, while transfer characteristics recovered after unloading. Combined mechanical and electrical stress enhanced PBTI degradation, consistent with stress-assisted carrier trapping. In WS2 FETs, local mechanical stress produced a fully recoverable gate-leakage response in one study, while vertical compression in another reduced on-current by up to approximately 74%, with mobility reduction identified as the dominant mechanism. The local-heater platform achieved localized temperature control of about 85 °C and extended the method to simultaneous thermal, mechanical and electrical assessment. The results provide a basis for stress-aware design and reliability qualification of IGZO-based memory and logic, two-dimensional devices, BEOL-compatible transistors and monolithic 3D technologies. Further uptake can build on continued device-level validation, expanded thermal-mechanical studies and translation of the methodology into future qualification workflows.