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European pilot line for beyond 2nm leading edge System-on-Chip leadership

Project description

Pioneering Europe’s semiconductor future

The global demand for faster, more efficient, and sustainable electronics is driving innovation in semiconductor technologies. Yet, Europe faces challenges in maintaining leadership in this critical domain, particularly with cutting-edge solutions like advanced logic, memory, and interconnect technologies. Emerging markets in computing, communication, mobility, energy, and health require groundbreaking advancements to stay competitive. To address these needs, the EU-funded NanoIC project aims to establish Europe’s first beyond-2 nm System-on-Chip (SoC) pilot line. It will deliver a 300 mm pilot line to the semiconductor ecosystem, advancing technologies such as nanosheet transistors, spintronic memory, and optical interconnects. With a strong focus on sustainability and collaboration, the project supports research, training, and innovation across Europe.

Objective

NanoIC will provide Europe with a beyond 2nm leading-edge SoC pilot line for advanced logic, memory and interconnect technologies to strengthen European leadership in advanced technologies development for markets like computing, communication, mobility, energy and health.
The objective of NanoIC is to deliver a 300mm pilot line to the entire semiconductor ecosystem to address the challenges defined in the CPL-1 call of the European Chips Act.
Technology development will go up to TRL 3-6 for (i) logic Nanosheet (NS, N2, A14, A10) and Complementary FET (CFET, A7 and beyond) device architectures and high-NA EUV; (ii) the advanced memory options Spin Orbit Torque (SOT)-MRAM, embedded DRAM and 3D-DRAM; (iii) advanced electrical and optical interconnects like die-to-wafer hybrid bonding, fine-pitch re-distribution layer technology chiplet enablement, laser die-to-wafer integration on 300mm photonic interposers.
Sustainability is a focus area aimed at energy efficiency, reduction of greenhouse gas emission and water usage of the baseline flows, supported by automated tool and process data acquisition.
PDKs on NanoIC baselines for academia, startups, SME’s and industry will be supported by a design enablement facility and training. These include design pathfinding PDKs for prototyping and DTCO at the device and circuit level, and system exploration PDKs for prototyping system functionality combining NanoIC and foundry technologies.
Dissemination, Exploitation and Communication actions will engage all stakeholders in pan-European collaborations expanding the community of interest for these advanced technologies. The NanoIC pilot line will build on the collaboration of imec, CEA-Leti (France), Fraunhofer-Gesellschaft (FhG, Germany), VTT (Finland), CSSNT (Romania) and Tyndall Institute (Ireland), but will offer many opportunities for projects with the wider R&D community.

Fields of science (EuroSciVoc)

Keywords

Programme(s)

Topic(s)

Funding Scheme

HORIZON-JU-RIA - HORIZON JU Research and Innovation Actions

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Call for proposal

(opens in new window) HORIZON-JU-Chips-2023-RIA-CPL

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Coordinator

INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM
Net EU contribution
€ 432 633 226,00
Address
KAPELDREEF 75
3001 Leuven
Belgium
Region
Vlaams Gewest Prov. Vlaams-Brabant Arr. Leuven
Activity type
Research Organisations
Links
Total cost
€ 521 031 451,25

Participants (5)