Advanced Photonic Integrated Circuits Pilot Line for Europe

Project Information

PIXEurope

Grant agreement ID: 101213727

DOI

10.3030/101213727

EC signature date 19 June 2025

Start date 1 June 2025

End date 31 May 2030

Funded under

• Digital, Industry and Space

Total cost

€ 176 054 649,60

EU contribution

€ 88 027 324,81

Coordinated by

FUNDACIO INSTITUT DE CIENCIES FOTONIQUES
Spain

Periodic Reporting for period 1 - PIXEurope (Advanced Photonic Integrated Circuits Pilot Line for Europe)

Reporting period: 2025-06-01 to 2026-05-31

Summary of the context and overall objectives of the project

Photonic Integrated Circuits (PICs) are a key enabling technology for communications, artificial intelligence, sensing, healthcare, security and augmented/virtual reality, with a global market projected to more than double by the end of the decade. Europe has invested significantly in PIC research, but this effort has historically been fragmented across separate chip design, fabrication, packaging and testing communities, hindering the standardisation and industrial scale-up needed to compete globally. The European Chips Act identifies this fragmentation as a strategic bottleneck for Europe's technological sovereignty.

PIXEurope addresses this challenge by building the world's first fully integrated, Open Access Pilot Line for PICs, bringing together Europe's leading research and technology organisations across the entire PIC value chain — from design and chip fabrication to hybrid integration, packaging, testing and reliability. The Pilot Line’s pathway to impact rests on three pillars: unifying this fragmented ecosystem under a single coordinated access point; investing in state-of-the-art equipment and standardised design tools to raise technologies from early maturity to industrial readiness; and training a skilled workforce able to sustain long-term European competitiveness in this critical field. By its conclusion, PIXEurope aims to give European companies, including SMEs and start-ups, practical, one-stop access to advanced PIC technologies, strengthening Europe's industrial autonomy and its position in a market expected to grow from around €14 billion in 2024 to over €35 billion by 2029.

Work performed from the beginning of the project to the end of the period covered by the report and main results achieved so far

During RP1 (M1–M12), PIXEurope's technical work concentrated on establishing the foundations of the distributed Pilot Line rather than delivering finished technologies - consistent with a first reporting period in a 60-month project.

Installation & infrastructure (WP3): Equipment procurement, cleanroom preparation and installation planning began across all equipment-buying partners, tracked via a new online equipment database (D3.1). Cleanroom modifications are at varying stages of readiness (e.g. VTT's DUV stepper and Ge/Si epitaxy lines, TEL Track and TXRF installations elsewhere); on-site qualification and acceptance (T3.2/T3.3) had not yet formally started by M12, in line with the original schedule.

Design (WP4): 83 building blocks were defined across 16 PDKs, with all foundry partners releasing at least one PDK version to the PIXEurope PDK server (SOI, SiN, InP, SiC, AlO, graphene, lithium niobate, colloidal quantum dots, mid-IR platforms). Progress against the M60 building-block target stands at 31%. A validation pipeline linking the PDK server to OpenEPDA was established.

Monolithic and hybrid platforms (WP5, WP6): Partners advanced platform-specific process development within their existing (150 mm) process lines - e.g. UTWENTE achieved 6 dB/m SiN propagation losses and sub-1 dB/cm losses in the UV-VIS range; CEA-LETI fabricated a combined 220 nm SOI/SiN stack. VTT demonstrated broadband 3–4 µm operation on its existing SOI platform and began work towards converting it to 200 mm wafers, in line with Milestone 12 (due M20). In WP6, initial proof-of-concept results were obtained for micro-transfer printing and LIFT-based hybrid integration (III-V, GaN, TFLN, CQDs, graphene, phase-change materials), though several integration routes remain in the optimisation or troubleshooting stage rather than demonstrated processes.

Packaging, test and reliability (WP7, WP8): WP7 defined initial multiphysics simulation approaches, reference assembly concepts and an early proof-of-concept for wafer-level chiplet transfer onto a glass interposer; most packaging tasks remain in the planning/architecture stage. WP8 has two of seven tasks underway (material/structure characterisation), with wafer-level test and reliability capabilities still in the tendering and set-up phase.

Demonstrators (WP9): The specification phase (T9.1) is active, with all eight demonstrators confirmed and their leads presenting initial concepts; functional testing and validation have not yet started, as scheduled.

Progress beyond the state of the art and expected potential impact (including the socio-economic impact and the wider societal implications of the project so far)

At this early stage, PIXEurope's results are best characterised as promising building blocks rather than established advances beyond the state of the art. A small number of individual results already compare favourably with published figures (e.g. UTWENTE's sub-1 dB/cm UV-VIS losses, VTT's broadband 3 µm SOI performance and initial work towards 200 mm wafer scale), but these are single-platform, single-partner results that have not yet been cross-validated, integrated into a packaged device, or demonstrated at pilot-line volumes. The pilot line's genuinely novel contribution so far is architectural rather than purely scientific: it is the first attempt to bring monolithic, hybrid, packaging and test capabilities for photonics together under one standardised Design Kit framework (PDKs/ADKs/TDKs) and one shared digital platform (PDK server, JePPIX DET), rather than any single breakthrough process.