During RP1 (M1–M12), PIXEurope's technical work concentrated on establishing the foundations of the distributed Pilot Line rather than delivering finished technologies - consistent with a first reporting period in a 60-month project.
Installation & infrastructure (WP3): Equipment procurement, cleanroom preparation and installation planning began across all equipment-buying partners, tracked via a new online equipment database (D3.1). Cleanroom modifications are at varying stages of readiness (e.g. VTT's DUV stepper and Ge/Si epitaxy lines, TEL Track and TXRF installations elsewhere); on-site qualification and acceptance (T3.2/T3.3) had not yet formally started by M12, in line with the original schedule.
Design (WP4): 83 building blocks were defined across 16 PDKs, with all foundry partners releasing at least one PDK version to the PIXEurope PDK server (SOI, SiN, InP, SiC, AlO, graphene, lithium niobate, colloidal quantum dots, mid-IR platforms). Progress against the M60 building-block target stands at 31%. A validation pipeline linking the PDK server to OpenEPDA was established.
Monolithic and hybrid platforms (WP5, WP6): Partners advanced platform-specific process development within their existing (150 mm) process lines - e.g. UTWENTE achieved 6 dB/m SiN propagation losses and sub-1 dB/cm losses in the UV-VIS range; CEA-LETI fabricated a combined 220 nm SOI/SiN stack. VTT demonstrated broadband 3–4 µm operation on its existing SOI platform and began work towards converting it to 200 mm wafers, in line with Milestone 12 (due M20). In WP6, initial proof-of-concept results were obtained for micro-transfer printing and LIFT-based hybrid integration (III-V, GaN, TFLN, CQDs, graphene, phase-change materials), though several integration routes remain in the optimisation or troubleshooting stage rather than demonstrated processes.
Packaging, test and reliability (WP7, WP8): WP7 defined initial multiphysics simulation approaches, reference assembly concepts and an early proof-of-concept for wafer-level chiplet transfer onto a glass interposer; most packaging tasks remain in the planning/architecture stage. WP8 has two of seven tasks underway (material/structure characterisation), with wafer-level test and reliability capabilities still in the tendering and set-up phase.
Demonstrators (WP9): The specification phase (T9.1) is active, with all eight demonstrators confirmed and their leads presenting initial concepts; functional testing and validation have not yet started, as scheduled.
