Periodic Reporting for period 1 - Codasip RISC-V Solution for High-end Processor IP (Codasip High-end processor IP and high-level design tools for RISC-V)
Período documentado: 2022-11-01 hasta 2023-10-31
Embedded processors are at the core of innovative technological advancements. There is a contact need to enhance their capacity for high speed, security, efficient power consumption, reliability in order to achieve technological advancements in many economic areas. Moreover, in the context where general purpose microprocessors can no longer serve the multiple needs of technology innovators, there is an increasing demand for custom made chips. An increasing number of leading companies seek alternative suppliers to source their custom designed processors, thus opening a unique market opportunity for new technology providers to enter this critically important market. As a result, main processor users established an open processor standard called RISC-V.
RISC-V (pronounced “risk-five”) is an open processor instruction set architecture (ISA) standard that can be freely used for any purpose, permitting anyone to design, manufacture, and sell RISC-V chips and software. It is designed to be useful in both high-performance computing and low-power embedded applications. Although RISC-V is open-source, to develop a processor requires very specific design expertise in several specialties: electronic logic, compilers, simulation, verification, embedded software, and debug. While RISC-V open Instruction Set Architecture (ISA) addresses the many problems of the semiconductor industry, it still faces its own challenges of the ecosystem immaturity, reliability and ability to accelerate design / time-to-market.
Codasip offers a unique combination of semiconductor processor IP based on the RISC-V open instruction set architecture (ISA) and high-level EDA tool Codasip Studio providing outstanding flexibility and 5x faster time to market. RISC-V ISA can be used for a wide variety of applications ranging from low power and low gate count embedded cores to advanced high frequency application cores.
RISC-V (pronounced “risk-five”) is an open processor instruction set architecture (ISA) standard that can be freely used for any purpose, permitting anyone to design, manufacture, and sell RISC-V chips and software. It is designed to be useful in both high-performance computing and low-power embedded applications. Although RISC-V is open-source, to develop a processor requires very specific design expertise in several specialties: electronic logic, compilers, simulation, verification, embedded software, and debug. While RISC-V open Instruction Set Architecture (ISA) addresses the many problems of the semiconductor industry, it still faces its own challenges of the ecosystem immaturity, reliability and ability to accelerate design / time-to-market.
Codasip offers a unique combination of semiconductor processor IP based on the RISC-V open instruction set architecture (ISA) and high-level EDA tool Codasip Studio providing outstanding flexibility and 5x faster time to market. RISC-V ISA can be used for a wide variety of applications ranging from low power and low gate count embedded cores to advanced high frequency application cores.
As part of this project, we are seeking to Take advantage of the new RISC-V market opportunity and to extend our portfolio of IP cores to include high-end high-performance compute area, complementing our cores that cover the power efficient embedded and mid range compute area: a new generation of advanced core with a 9-stage pipeline with out-of -order superscalar architecture called A900.
We expect that the release of A900 will lead towards the A1100 core with heavily speculative execution and an 11-stage pipeline. In addition to the design of these cores, we seek to release of Codasip Studio processor design tool for high-end compute, including advanced features like support of out of order architectures.
As the project is still in progress as on October 2023, we expect to give an update on project results and main achievements towards the final stages of the project.
We expect that the release of A900 will lead towards the A1100 core with heavily speculative execution and an 11-stage pipeline. In addition to the design of these cores, we seek to release of Codasip Studio processor design tool for high-end compute, including advanced features like support of out of order architectures.
As the project is still in progress as on October 2023, we expect to give an update on project results and main achievements towards the final stages of the project.
Significant progress was made in advancing the Codasip Studio tool, including the web-based IDE, workspaces, and containers for EDA tools. Development of related tutorials and user documentation also complement the technology.
Development of High-end RISC-V cores and functional safety and cybersecurity standards compliance will complement the technological progress delivered so far.
In addition, we managed to scale up the company by enhancing internal process management, HR, legal and finance processes, while also expanding our international presence with new offices in Europe and Asia.
Development of High-end RISC-V cores and functional safety and cybersecurity standards compliance will complement the technological progress delivered so far.
In addition, we managed to scale up the company by enhancing internal process management, HR, legal and finance processes, while also expanding our international presence with new offices in Europe and Asia.