Codasip High-end processor IP and high-level design tools for RISC-V

Informazioni relative al progetto

Codasip RISC-V Solution for High-end Processor IP

ID dell’accordo di sovvenzione: 190101116

DOI

10.3030/190101116

Progetto chiuso

Data della firma CE 26 Ottobre 2022

Data di avvio 1 Novembre 2022

Data di completamento 31 Luglio 2025

Finanziato da

• The European Innovation Council (EIC)

Costo totale

€ 21 523 750,00

Contributo UE

€ 2 499 999,00

Coordinato da

CODASIP GMBH
Germany

Periodic Reporting for period 2 - Codasip RISC-V Solution for High-end Processor IP (Codasip High-end processor IP and high-level design tools for RISC-V)

Periodo di rendicontazione: 2023-11-01 al 2025-07-31

Sintesi del contesto e degli obiettivi generali del progetto

Embedded processors are at the core of innovative technological advancements. There is a contact need to enhance their capacity for high speed, security, efficient power consumption, reliability in order to achieve technological advancements in many economic areas. Moreover, in the context where general purpose microprocessors can no longer serve the multiple needs of technology innovators, there is an increasing demand for custom made chips. An increasing number of leading companies seek alternative suppliers to source their custom designed processors, thus opening a unique market opportunity for new technology providers to enter this critically important market. As a result, main processor users established an open processor standard called RISC-V.

RISC-V (pronounced “risk-five”) is an open processor instruction set architecture (ISA) standard that can be freely used for any purpose, permitting anyone to design, manufacture, and sell RISC-V chips and software. It is designed to be useful in both high-performance computing and low-power embedded applications. Although RISC-V is open-source, to develop a processor requires very specific design expertise in several specialties: electronic logic, compilers, simulation, verification, embedded software, and debug. While RISC-V open Instruction Set Architecture (ISA) addresses the many problems of the semiconductor industry, it still faces its own challenges of the ecosystem immaturity, reliability and ability to accelerate design / time-to-market.

Codasip offers a unique combination of semiconductor processor IP based on the RISC-V open instruction set architecture (ISA) and high-level EDA tool Codasip Studio providing outstanding flexibility and 5x faster time to market. RISC-V ISA can be used for a wide variety of applications ranging from low power and low gate count embedded cores to advanced high frequency application cores.

Lavoro eseguito dall’inizio del progetto fino alla fine del periodo coperto dalla relazione e principali risultati finora ottenuti

The project successfully advanced Codasip’s processor design capabilities by developing a robust ecosystem for high-performance RISC-V cores and their supporting EDA tools.

The team designed two complex out-of-order architectures—A90 and A110—targeting AI, IoT, and data-intensive applications. These cores include scalable memory systems, advanced vector and floating-point units, and replay-based performance models, enabling precise architectural tuning and formal verification strategies. The team did not complete the verified design of the A90 processor on time, which is reported as a deviation against the original project scope.

To support this innovation, Codasip Studio was significantly enhanced. The desktop version introduced CodAL 3.0 a high-level architecture description language with constructs for auto-pipelining, data hazards, and cache coherency. Software Development (SDK) and Hardware Development Kit (HDK) generators were reengineered to support these features, and a modern IDE based on Visual Studio Code was integrated for improved usability.

Parallel to this, a web-based Codasip Studio was developed using Kubernetes and Eclipse Theia, offering scalable, isolated cloud workspaces. This platform supports multiple toolchains, real-time syntax feedback, and advanced debugging, making processor design accessible and efficient across user profiles.

In functional safety and cybersecurity, Codasip achieved ISO 26262 and ISO/SAE 21434 certifications. A structured safety framework was implemented, validated through pilot projects, and independently assessed by TÜV SÜD. Additionally, a Security Pack was delivered, including Secure Boot and TRNG components, enabling secure and compliant hardware IP for safety-critical applications.

Progressi oltre lo stato dell’arte e potenziale impatto previsto (incluso l’impatto socioeconomico e le implicazioni sociali più ampie del progetto fino ad ora)

Since the project beginning, the market has been dominated by a few major players offering proprietary processor architectures. The open RISC-V ISA was seen as a disruptive force, particularly in the low-to-mid performance segment.

Codasip aimed to extend this disruption into the high-performance domain, not only through core development but also by democratizing processor design via cloud-based automation tools in Studio. This approach was expected to lower entry barriers, enabling innovation from a broader range of engineers and institutions across Europe.

Over the course of the project, significant progress was made in high-performance RISC-V architecture, with specifications for two processors completed. Although verified designs are still pending, the strategic importance of serving the European market has grown substantially due to evolving geopolitical conditions. Codasip’s work contributes to the localization of the semiconductor value chain and supports European technological autonomy, aligning with broader EU priorities.

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