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Optical Interconnections for VLSI and Electronic Systems

Objective

The overall objective of OLIVES was to develop optical interconnections for use in advanced electronic computer and processor systems that were expected to significantly improve performance compared with the electrical alternative. The project linked four of Europe's leading optical, semiconductor and computer companies with a chemical company and five universities, and aimed towards the commercial exploitation in high-performance processors from the mid-1990s onwards.
The overall objective of OLIVES was to develop optical interconnections for use in advanced electronic computer and processor systems, that were expected to significantly improve performance compared with the electrical alternative. The project focused on the development, construction and assessment of a set of demonstrators which acted as test beds for 2-dimensional and 3-dimensional optical interconnections. These demonstrators covered the application of optics to both clock and data distribution at the chip, board and interboard levels.
Significant advances were made in the enabling technologies of holography, silica on silicon waveguides, precision mounting of optical elements, optical Stark modulators, detector arrays, and receiver and driver arrays in emitter coupled logic (ECL) and complementary metal oxide semiconductor (CMOS). A first prototype based on the optical mastercard was constructed. Clear applications for the gallium arsenide on silicon technology in optical motherboards and optoelectronics CMOS were identified, and collaborative research and development established. The development of stable cross linked polymers for waveguides and modulators also opened up many new possibilities. Overall, it has become clear that the comparison of optical and electrical interconnects is very system specific and a scheme which offers no advantages in one system may be very advantageous in another, depending on the precise system requirements.
Results for the major demonstrators are as follows: the optimum fanout range for the chip level optical clock distribution (chip area to area demonstrator) network was found to lie between 10 and 100; the benefits of chip area to area interconnects were considered in the context of neural networks where simulations of a 1000-node system showed a potential performance gain of several hundred; the optical bus would be used for the interconnection of several nodes and shared store in a coarse grain multiprocessor mainframe co mputer; the full benefit of the mastercard interconnects in the context of real time processors is the reduction in the volume occupied by the interconnection medium.
Finally, studies of the potential applications for optics to back plane busses in large departmental servers and asynchronous transfer mode (ATM) switches are initiated.
The project focused on the development, construction and assessment of a set of demonstrators which acted as test-beds for two- and three-dimensional optical interconnections. These demonstrators covered the application of optics to both clock and data distribution at the chip, board and inter-board levels.

To provide the components required for these demonstrators a significant technological effort was made in the fields of holography, guided wave components, receiver circuitry and optical modulators. In addition, precision alignment and hybridisation techniques for both the mounting of the optoelectronic components and the registration of the boards themselves were developed.

In view of the present state of the art in the monolithic integration of active optical components and silicon circuitry, hybrid optoelectronic integration was used throughout the demonstrator construction phase. However, monolithic integration may offer great potential advantages, and in parallel with the demonstrator development a study of the growth of III-V compounds on silicon was undertaken. In addition, a study of polymeric materials for optical modulators is being included, since these may offer significant advantages over alternative techniques.

Coordinator

BNR Europe Ltd
Address
London Road
CM17 9NA Harlow
United Kingdom

Participants (9)

AKZO INTERNATIONAL RESEARCH
Netherlands
Address
Velperweg 76
6824 BM Arnhem
CENTRO NACIONAL DE MICROELECTRONICA
Spain
Address
Serrano, 144
28006 Madrid
EIDGENOESSISCHE TECHNISCHE HOCHSCHULE
Switzerland
Address
Eth-hoenggerberg Hpt
8093 Zurich
FORTH RESEARCH CENTER OF CRETE
Greece
Address
Madzapetaki, 21, 1385
71110 Heraklion
GEC Plessey Semiconductors plc
United Kingdom
Address
Caswell
NN12 8EQ Towcester
Interuniversitair Mikroelektronica Centrum
Belgium
Address
Kapeldreef 75
3030 Heverlee
Siemens AG
Germany
Address
Otto-hahn-ring 6
81739 München
Thomson CSF
France
Address
Domaine De Corbeville
91404 Orsay
Birkbeck College, University of London
United Kingdom
Address
Malet Street, Bloomsbury
WC1E 7HX London