Project description FET proactive 1: Concurrent Tera-device Computing Show the project objective Hide the project objective Technology projections indicate that future electronic devices will keep shrinking, being faster and consuming less energy per operation. In the next decade, a single chip will be able to perform trillions of operations per second and provide trillions of bytes per second in off-chip bandwidth. This is the so called Terascale Computing era, where terascale performance will be mainstream, available in personal computer, and being the building block of large data centers with petascale computing capabilities. However, these smaller devices will be much more susceptible to faults and its performance will exhibit a significant degree of variability. As a consequence, to unleash these impressive computing capabilities, a major hurdle in terms of reliability has to be overcome. The TRAMS project is the bridge for reliable, energy efficient and cost effective computing in the era of nanoscale challenges and teraflop opportunities.The International Roadmap for Semiconductors (ITRS) report indicates that the Metal Oxide Semiconductor devices (MOS or MOS like devices) will be ultimately scaled down below 10 nm in several years. The CMOS technologies after the 16 nm technology generation are called Late CMOS technologies and will include novel multigate device architectures and novel channel and gate stack materials. Reliability issues are expected to be exacerbated to in sub-10 nm CMOS technology.Beyond-CMOS emerging technologies will reach device dimensions reduction below 5 nm utilising among others, nanowire transistors, quantum devices, carbon nanotubes, graphene, or molecular electronics. Both the Late CMOS and the Beyond CMOS technologies hold the promise of a significant increase in device integration density complemented by an increase in system performance and functionality. However, a dramatic reduction in single device quality is also expected, complemented by increase in statistical variability, severe reduction of the signal to noise ratio, and severe reliability problems. Therefore,alternative device solutions and computation paradigms need to be investigated to keep the technology evolution pace in such a challenging scenario. Memory cells and, in general, system architectures intended for nanotechnologies (both late CMOS and emerging devices) need to address the variability and reliability problem and should be capable of solving or at least largely alleviating it. In order to build reliable nanosystems, the TRAMS project addresses a specific variability and reliability-aware analysis and design flow as well as a hierarchical tolerance design. In such a tera-device multicore system the main idea will be to define countermeasure techniques at circuit and architecture design levels. The objective of this project is to investigate in depth potential new design alternatives and paradigms, which will be able to provide reliable memory systems out of highly unreliable nanodevices at a reasonable cost and design effort. Fields of science engineering and technologynanotechnologynano-materialstwo-dimensional nanostructuresgraphenenatural scienceschemical sciencesinorganic chemistryinorganic compoundsnatural sciencesphysical scienceselectromagnetism and electronicssemiconductivity Programme(s) FP7-ICT - Specific Programme "Cooperation": Information and communication technologies Topic(s) ICT-2009.8.1 - FET proactive 1: Concurrent Tera-device Computing Call for proposal FP7-ICT-2009-4 See other projects for this call Funding Scheme CP - Collaborative project (generic) Coordinator UNIVERSITAT POLITECNICA DE CATALUNYA EU contribution € 860 889,00 Address CALLE JORDI GIRONA 31 08034 Barcelona Spain See on map Region Este Cataluña Barcelona Activity type Higher or Secondary Education Establishments Administrative Contact VALENTI GUASCH BRULL (Mr.) Links Contact the organisation Opens in new window Website Opens in new window Total cost No data Participants (3) Sort alphabetically Sort by EU Contribution Expand all Collapse all INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM Belgium EU contribution € 590 900,00 Address KAPELDREEF 75 3001 Leuven See on map Region Vlaams Gewest Prov. Vlaams-Brabant Arr. Leuven Activity type Research Organisations Administrative Contact Christine Van Houtven (Ms.) Links Contact the organisation Opens in new window Website Opens in new window Total cost No data INTEL CORPORATION IBERIA SA Spain EU contribution € 498 785,00 Address PLAZA PABLO RUIZ PICASSO 1 EDIFICIO TORRE PICASSO PLANTA 25 28020 Madrid See on map Region Comunidad de Madrid Comunidad de Madrid Madrid Activity type Private for-profit entities (excluding Higher or Secondary Education Establishments) Administrative Contact Antonio Gonzalez (Dr.) Links Contact the organisation Opens in new window Total cost No data UNIVERSITY OF GLASGOW United Kingdom EU contribution € 499 400,00 Address UNIVERSITY AVENUE G12 8QQ Glasgow See on map Region Scotland West Central Scotland Glasgow City Activity type Higher or Secondary Education Establishments Administrative Contact Derek Motherwell (Mr.) Links Contact the organisation Opens in new window Website Opens in new window Total cost No data