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Rendering FPGAs to Multi-Core Embedded Computing

Description du projet


Computing Systems
To develop an approach and a tool-chain to improve productivity by accelerating development cycles of reconfigurable systems by more than two orders of magnitude
The ever increasing need for additional product functionalities, safety, and security, drives many product suppliers towards the need for more and more platform performance. For instance, next-generation UAVs (unmanned aerial vehicles) are expected to be much more complex in terms of sensing. As such, the analysis and decision-making processes will lead to a higher performance requirement, together with the need of low cost solutions. Another example is audio encoding, where better performance and improved encoding quality are features of major interest. While these requirements are met by implementing as many functions as possible in hardware it is certainly desirable to host product functionalities on as few hardware platforms as possible in order to reduce size, weight and power of products.
Reconfiguration has been recognized as a key technique to achieve these goals. However, designing reconfigurable systems is an extremely cumbersome and error-prone process. As a result, the potential of reconfiguration is only achieved at high design effort and cost.
REFLECT aims at developing an approach and a tool-chain to improve productivity by accelerating development cycles of reconfigurable systems by more than two orders of magnitude.

The relentless increase in capacity of Field-Programmable Gate-Arrays (FPGAs) makes them vehicles of choice for both prototypes and final products requiring on-chip multi-core, heterogeneous and reconfigurable systems. Multiple cores can be embedded as hard- or soft-macros, have customizable instruction sets, multiple distributed RAMs and/or configurable interconnections. Their flexibility allows them to achieve orders of magnitude better performance than conventional computing systems via customization. Programming these systems, however, is extremely cumbersome and error-prone and as a result their true potential is only achieved at an unreasonably high effort.This project will develop, implement and evaluate a novel compilation and synthesis system approach for FPGA-based platforms. We rely on Aspect-Oriented (AO) Specifications to covey critical domain knowledge to a mapping engine while preserving the advantages of a high-level imperative programming paradigm in early software development and portability. We leverage AO specifications and a set of transformations to generate an intermediate representation using an extensible mapping language (LARA). LARA specifications will allow the exploration of alternative architectures and run-time adaptive strategies enabling the generation of flexible hardware cores that can be easily incorporated into larger multi-core designs. We will evaluate the effectiveness of the proposed approach using partner-provided codes from the domain of audio/video processing and real-time avionics.We expect the technology developed here to be integrated by our industrial partners, a leading compilation tool supplier for reconfigurable systems and a worldwide solution supplier of embedded high-performance systems. The academic partners will promote human resources with technical excellence in the area of architectures and software development thus enabling the sustainability of a vibrant information technology European fabric.

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Coordinateur

HONEYWELL INTERNATIONAL SRO
Contribution de l’UE
€ 260 525,00
Adresse
V PARKU 2325/16 CHODOV
148 00 PRAHA
Tchéquie

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Région
Česko Praha Hlavní město Praha
Type d’activité
Private for-profit entities (excluding Higher or Secondary Education Establishments)
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