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Steep subthreshold slope switches\nfor energy efficient electronics

Project description

Nanoelectronics Technology
European Union Research Initiative Aims to Increase 
Electronic Device Efficiency by 10x and Eliminate Power Consumption of Devices in Standby Mode
STEEPER addresses the development of Beyond CMOS energy-efficient steep subthreshold slope transistors based on quantum mechanical band-to-band tunnelling (tunnel FETs), with the aim of reducing the operation voltage of nanoelectronic circuits to sub-0.5V and their power consumption by one order of magnitude.STEEPER focuses on two technology tracks, united by same device principle, shared performance boosters, and compatibility with silicon CMOS. These are (i) Ultra-Thin-Body Silicon-On-Insulator technology for planar, tri-gate and nanowire tunnel FETs featuring ultra-low standby power and smartly exploiting additive boosters: high-k dielectrics, SiGe source, strain, and improved electrostatic design, and (ii) a III-V nanowire platform on silicon, as unique material to control staggered or broken bandgap boosters and devise a high performance (high-Ion, steep slope) implementation of tunnel FETs. Platform (i) will enable a hybrid platform combining high performance (HP) CMOS and low standby power (LSTP), low voltage tunnel FETs, supporting energy efficient hybrid CMOS/Tunnel-FET digital and analog/RF circuit design. In line with ITRS, STEEPER will evaluate in platform (ii) the physical and practical limits of boosting the performance of tunnel FETs with III-V nanowires on silicon, and resulting advantages for HP digital circuits.The development of the two technology platforms are interactive and collaborative in terms of performance boosters, and will benefit from simulation and modelling support by the academic partners, and from investigation of the potentially critical variability and sensitivity of tunnel FETs. Industrial benchmarking is proposed at device and circuit levels by the key involved industries, and the figures of merit of hybrid CMOS/tunnel FET digital and analog circuit design will be investigated.The project targets energy efficient nanoelectronic technology for high volume markets covering digital, analog/RF and mixed mode applications.

STEEPER addresses the development of Beyond CMOS energy-efficient steep subthreshold slope transistors based on quantum mechanical band-to-band tunnelling (tunnel FETs), with the aim of reducing the operation voltage of nanoelectronic circuits to sub-0.5V and their power consumption by one order of magnitude.STEEPER focuses on two technology tracks, united by same device principle, shared performance boosters, and compatibility with silicon CMOS. These are (i) Ultra-Thin-Body Silicon-On-Insulator technology for planar, tri-gate and nanowire tunnel FETs featuring ultra-low standby power and smartly exploiting additive boosters: high-k dielectrics, SiGe source, strain, and improved electrostatic design, and (ii) a III-V nanowire platform on silicon, as unique material to control staggered or broken bandgap boosters and devise a high performance (high-Ion, steep slope) implementation of tunnel FETs. Platform (i) will enable a hybrid platform combining high performance (HP) CMOS and low standby power (LSTP), low voltage tunnel FETs, supporting energy efficient hybrid CMOS/Tunnel-FET digital and analog/RF circuit design. In line with ITRS, STEEPER will evaluate in platform (ii) the physical and practical limits of boosting the performance of tunnel FETs with III-V nanowires on silicon, and resulting advantages for HP digital circuits.The development of the two technology platforms are interactive and collaborative in terms of performance boosters, and will benefit from simulation and modelling support by the academic partners, and from investigation of the potentially critical variability and sensitivity of tunnel FETs. Industrial benchmarking is proposed at device and circuit levels by the key involved industries, and the figures of merit of hybrid CMOS/tunnel FET digital and analog circuit design will be investigated.The project targets energy efficient nanoelectronic technology for high volume markets covering digital, analog/RF and mixed mode applications.

Fields of science

Programme(s)

Topic(s)

Call for proposal

FP7-ICT-2009-5
See other projects for this call

Funding Scheme

CP - Collaborative project (generic)

Coordinator Contact

Mihai Adrian IONESCU Prof.

Coordinator

ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE
Address
Batiment ce 3316 station 1
1015 Lausanne
Switzerland

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Region
Schweiz/Suisse/Svizzera Région lémanique Vaud
Activity type
Higher or Secondary Education Establishments
Links
EU contribution
€ 484 540,00

Participants (13)

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Last update: 1 August 2019

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Permalink: https://cordis.europa.eu/project/id/257267

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