Final Report Summary - HITME (High Temperature Electronics)
Executive Summary:
The prime aim of the HiTME project has been to develop a safety-critical electronic system which can operate reliability when installed in the severe engine core environment. Central to this objective, will be the development of electronic components and material technologies along with smart thermal and packaging designs that make the concept feasible.
In order to design a product capable of withstanding the high temperatures associated with an engine core installation, whilst still maintaining performance (accuracy) and life, fundamental advancement in key technological areas were necessary to investigate.
The following areas were seen as the underpinning building blocks to ‘enable’ a new generation product and that formed the core of the research activity.
• Component Enhancement (HTSOI, SiC & Passive Components)
• Thermal Design (Cooling Technologies)
• Material Selection (Material Technologies)
• Packaging / Installation Design (Novel Packaging)
• Develop Test Methods (and Analyses)
The work was apportioned in the consortium as follows:-
AEC - Management
Operational environment
Electronics and mechanical design
Test methods and analysis
Raytheon - Concept design
SiC CMOS integrated circuit design and manufacture
TWI limited - Materials Evaluation
- Thermal management solutions
Cissoid S.A. - SOI integrated circuit supply and characterisation
Passive component characterisation
Project Context and Objectives:
Introduction
To establish knowledge in key areas of high temperature electronics development, the project integrates the design, development and test of leading edge materials and electronic components with novel test methods. These activities, augmented by academic paper research, will deliver a combination of test vehicles to evaluate material technology, manufacturing process, and life expectancy of representative elements from an engine control system, capable of fulfilling today and tomorrow’s engine needs.
The goal of the research program was to design an engine control sub-system utilising, currently available, High Temperature Silicon-on-Insulator (“HTSOI”) and/or Silicon Carbide (“SiC”) components. Where components necessary for the development of key engine control functionality are not currently available or cannot effectively be thermally managed, bespoke SiC, Complementary Metal Oxide Semiconductor (“CMOS”) devices will be specifically designed and characterised by Raytheon Systems Limited (“RSL”).
The majority of civil ECUs are installed on the engine fan-case. While this location is certainly harsh with respect to vibration and temperature transients, it is unlikely that any electronic products designed today, for installation on the fan-case, would survive at the extreme temperatures generated by the engine core. There is therefore a significant gap between the future engine need and current state-of-the-art when viewed at the ECU product level.
However, for many of the research objectives defined, progress beyond the current state-of-the-art, in that particular discipline, is anticipated. The individual advances in these key technological areas will be combined and integrated to develop a new generation ECS which will, itself, progress beyond the current ECU capability.
Therefore, in order to design a product capable of withstanding the high temperatures associated with an engine core installation, whilst still maintaining similar performance (accuracy) and life, fundamental advancement in key technological areas will be necessary. The following areas are seen as the underpinning building blocks that will enable a new generation product.
• Component enhancement (HTSOI, SiC & passive components)
• Thermal design (cooling technologies)
• Material selection (material technologies)
• Packaging / installation design (novel packaging)
• Develop test methods (and analyses)
Component Enhancement
Electronic component technology exists today, which is capable of operation to 2250C, albeit with a short life, not consistent with aerospace maintenance practice. Cissoid is a major player in the high temperature electronics market, having developed a range of components using a HTSOI process. A number of these components are of use to an engine control system designer, but many key component types are currently unavailable.
There is also a limited, but expanding, market of electronic components, based upon SiC technology, which can operate successfully to temperatures in excess of 300 Deg C for periods of time consistent with aircraft maintenance practices. Unfortunately, the functionality afforded by this technology is yet to move beyond basic switching components for high power application. Through a number of prior research programmes, RSL has developed a SiC CMOS process capable of >300 Deg C operation. This provides an opportunity to develop more complex components, such as sensor amplifiers, currently unavailable in SiC technology.
Degradation in the performance of passive components at elevated temperature is well understood from basic physics. Capacitors, in particular, exhibit poor charge retention at high temperature which results in a very large de-rating at the circuit design level, which ultimately leads to much larger large components. Cissoid has experience with a new technology of capacitors which show reliable performance at elevated temperatures.
Thus, in the area of component enhancement, the challenge for the project was three-fold:
• To develop a system design using component parts which are not rated to operate at extreme temperatures, by a combination of parameter de-rating and active thermal design. This work will be carried out in work packages 3.4 and 4.1 circuit block development’ and ‘evaluate thermal management solutions’.
• To rigorously examine the HTSOI process to understand the constraints and failure mechanisms associated with operation beyond current rated temperatures. This activity will include component characterisation and qualification and will be carried out in work package 3.2; further detail is provided below.
• To evaluate and characterise component technologies which can operate at the required temperatures. Two separate component technology development activities will be carried out as part of this program. SiC CMOS integrated circuits will be developed as part of work package 3.1. Temperature capable chip capacitors will be characterised as part of work package 3.3; further detail is provided below.
Characterisation and Qualification of HTSOI Components
Testing previously performed by Cissoid appears to indicate that the potential of HTSOI technology is yet to be fully exploited. Tests carried out to date confirm that HTSOI based circuits can operate at 250ºC and survive excursions up to 375ºC. However, these components have not been fully characterised and qualified for operation at the temperatures applicable to core engine electronics. It is the prime goal of Cissoid to develop the required know-how to develop the test methods and vehicles necessary for this qualification. An important element in the qualification process will be a rigorous examination of HTSOI components to understand the constraints and failure mechanisms associated with operation beyond the rated temperatures. Once a characterisation / qualification method has been established, it may then be used to validate the performance of other electronic components such as passive components. The final objective is to establish characterisation at component level for use by the system designer, to optimise performance and efficiency of a complete sub-system, at the design stage.
Development of SiC Components
RSL has already demonstrated state of the art through the development of n and p type FET transistors on SiC which have been tested up to 350 Deg C (Reference Clark et al, ECSCRM Oslo, Aug 31 2010). A simple ring oscillator integrated circuit (900 transistors) has also been demonstrated at 300 Deg C. Work continues to develop an even higher temperature capable process. The benefits of such a high temperature process are three-fold:
• The ability to offer active electronics solutions in extreme environments [>300 Deg C]
• The ability to accelerate life test on active electronics for lower temp operation [200 to 300 Deg C]
• The possibility to offer extended life electronics over current state of the art at 225 Deg C.
Existing silicon based state of the art from commercially available semiconductor processes provides junction temperatures up to 2250C (Reference: X-Fab 1u HT SOI process). There has been research into the use of other semiconductor materials for high temperature applications including GaN, GaAs and Diamond. These do not hold out so much promise, or are significantly less mature than the SiC CMOS demonstrated by RSL. Other SiC based state of the art includes lower capability NMOS and JFET based research presented recently by NASA, General Electric and Bosch groups.
High Temperature Characterisation of Chip Capacitors
New technology capacitors with very interesting properties at high temperature have been recently identified by Cissoid. These capacitors are thought to have a close match to active HTSOI devices and are therefore expected to benefit from extended temperature stability.
When compared with ceramic chip capacitors, typically used for high temperature applications, these components offers high temperature stability, lower leakage, higher density and potentially a very good reliability. The selection and validation of packaging techniques suitable for operation at high temperatures will be the key element of this activity.
Thermal Design
Thermal management has become a significant issue in recent generations of ECUs and for future systems this will likely become a product differentiator; there are two key considerations;
• Rising density, clock speeds and power of electronic components, leading to increasing demands for dissipation of the waste heat generated (Internal Source)
• Increased application of electronics to harsh temperature environments. (External Source)
If thermal management design is inadequate, premature component failure can be expected wither by direct failure of the semiconductor or, more likely, by progressive accumulation of thermo-mechanical damage and eventual cracking of the interconnect structures. To date industry have developed solutions based on new materials for heat-sinks and heat spreaders, interface materials or joints for thermally efficient assembly of components. While these solutions have allowed an extension of the range of passive cooling, an increasing demand in aerospace applications has driven the development of new active cooling systems, which have ramifications in terms of cost, complexity and reliability.
This project has tried to address the total thermal management system: junction through to die to package to board/substrate to enclosure to external environment. Novel cooling and insulation approaches and assessment of the feasibility of using SMART electronics to protect more sensitive components and reduce internal heat generation at key times have been examined in the project.
TWI and Aero Engine Controls have extensive experience in both the thermal management in current aerospace engine control products and the technologies used in other sectors such as automotive, computer and oil & gas. TWI is also developing novel textured heat exchange surfaces, heat-sink systems and spray coated thermally conducting/insulating interface materials which will be assessed for this application.
Material Selection
Conventional consumer electronics operate at temperatures in the range 0 - 70°C. This enables extensive use of polymer based attachment and encapsulation systems, printed circuit board technology and solder package attachment systems. These materials, packaging and production assembly processes have been refined over the last 30 years and have resulted in relatively high reliability products for their operational/design life which may be only 2 - 5 years.
These techniques, together with the more expensive ceramic, glass and metal housed ‘high reliability systems’ have been developed for sectors, such as aerospace, to operate at ambient temperatures of 125°C for significantly longer periods of time (e.g.20 years). However, above these temperatures there are significant concerns as to the performance of these materials and their associated interconnect systems, for example:
To operate at ambient temperatures of 250°C with transients up to 300°C this project will implement a step change in package material and interconnect technologies.
Success will be achieved by establishing combinations of materials and interconnect systems that are compatible metallurgically, chemically, mechanically and electrically, while subjected to an engine core environment.
Packaging and Installation Design
Currently ECU’s are mounted on the engine fancase, isolated from engine vibration by the use of elastometric anti-vibration (“AV”) mounts. When moving closer to the engine core (i.e. higher operating temperature environments) these materials are no longer suitable but there are all-metal solutions which have been used in aerospace and off-shore oil/gas applications which may be suitable at increased temperatures. An alternative approach has been consideered, made feasible by the reduction in size and weight of a disbursed node ECU, is to hard-mount the ECU directly to the engine metalwork.
Disbursed nodes could either be in the form of an autonomous line replaceable unit (see adjacent picture) or form part of a ‘smart’ hydro-mechanical system (see picture below). The latter involves more complex integration activities but may provide a simpler and cheaper solution to the end customer.
In each case it was important to consider external interconnect (harnessing and connectors), mounting and the provision of a good grounding path for electro magnetic compatability (“EMC”) and lightning strike threats. Conventional ECU external connectors are capable of 260°C but tend to be large and heavy designs.
For high temperature micro-electronic packages, smaller connectors such as micro-D or nano, might be better suited to keep to size and weight of the unit down. Interconnect can be made via direct wire bond on substrate or high temperature printed circuit board (PCB) connectors with flex or wire.
Selecting the right materials is key to packaging design. Normally aluminium would be selected for its light weight and high thermal conductivity, but at elevated temperatures the material properties (e.g. strength) will be affected; this may see a move more towards steel, kovar or titanium. It is important to understand and consider how all the materials that makes up an assembly, react to each (e.g. thermal expansion matching and galvanic corrosion).
Environmental protection is another factor to consider in the packaging design; traditionally fluorosilicone (fuel resistant) seals would be used to restrict fluid ingress and sand/dust. The trend for micro-electronics is to make the design hermetic; this results in a cleaner (and potentially more reliable) internal environment, but at an additional cost.
Statistical Validation of Life Test Methods
Testing is a critical issue for this development as the requirements will stretch the operating conditions well beyond conventional limits, especially for resilience to temperature and vibration, such that established data cannot be used and additional new test techniques will be required.
In particular, lifetime assessment is usually based on extrapolation of data from tests performed under conditions of accelerated stress, especially for temperature and temperature cycling range. So this presents a challenge for acceleration of tests for high operating temperatures – as there is a risk of moving into regimes of unrepresentative failure modes. Additional tests will be required to establish changes in material structures and properties at critical interfaces which will be essential to map out safe operating conditions and employ physics of failure principles – data on bulk properties are inadequate for this characterisation.
Improvements are also required in the time taken to achieve results during development. Even with highly accelerated stress acceleration, conventional reliability testing such a thermal cycling can take many thousands of hours to perform and then only produce a pass/fail result of limited value. Test techniques are required which produce measurements in real time such that degradation trends are identified early rather than just failure points, and test times can be reduced. The following were considered:-
• Precision reliability testing employs real-time electrical parameter measurement to identify degradation trends during a thermal cycling regime which is controlled with high precision to improve the scatter in results for more precise and faster predictions of lifetime
• Electro migration testing combines thermal and voltage stresses to identify the physical and electrical stability of conductors and dielectrics for both semiconductor components and interconnect substrates – a known problem for high temperature electronics.
• Nano-indentation is a high precision technique for determining the elastic and plastic characteristics of materials which have been subjected thermo-mechanical stresses and are in the process of degradation. This technique is especially appropriate for joints and provides essential input into physics of failure maps and lifetime prediction e.g. creep and fatigue resistance.
• As material properties change at elevated temperatures, combinational testing is very important. Vibration at temperature is an essential test technique for overall assemblies but needs refinement and application to identify critical resonant frequency responses at temperature for key components such as micro interconnect in cavity packages.
• Neural network test data acquisition is one possible technique for rapid collection and assimilation of data in real-time which may significantly enhance capability and reduce test times.
Project Results:
1 Introduction
The prime aim of the HiTME project is to develop a safety-critical electronic system which can operate reliability when installed in the severe engine core environment. Central to this objective, will be the development of electronic components and material technologies along with smart thermal and packaging designs that make the concept feasible.
In order to design a product capable of withstanding the high temperatures associated with an engine core installation, whilst still maintaining performance (accuracy) and life, fundamental advancement in key technological areas are necessary.
The following areas were seen as the underpinning building blocks to ‘enable’ a new generation product and that formed the core of the research activity.
• Component Enhancement (HTSOI, SiC & Passive Components)
• Thermal Design (Cooling Technologies)
• Material Selection (Material Technologies)
• Packaging / Installation Design (Novel Packaging)
• Develop Test Methods (and Analyses)
These tasks were set out in the work package descriptions of “JTI-CS-2010-4-SAGE-03-05” and the work carried out in response to the Description of Work is summarised in this report. The work was apportioned between AEC and the other partners in the HiTME consortium as follows…
AEC - Management
Operational environment
Electronics and mechanical design
Test methods and analysis
Raytheon - Concept design
SiC CMOS integrated circuit design and manufacture
TWI limited - Materials Evaluation
- Thermal management solutions
Cissoid S.A. - SOI integrated circuit supply and characterisation
Passive component characterisation
1 Work Package Descriptions and Work Undertaken
1.1 WP1 Operational Environment
This work package (WP) defined the environment within which the electronic unit, parts and processes were specified to operate. This included the temperature and vibration environment at various locations within the core mounted accessories zone(s) of the engine. Further definition was made in relation to the chosen function for demonstration derived from WP2 Concept Design.
The environment definition was reported in subsequent issues of report JTT114/0003. The HiTME programme [JTI-CS-2010-4-SAGE-03-05] defines the operating environment for any core mounted system as having a maximum steady state temperature of 250˚C with transient excursions to 300˚C. The analysis of PSRD data and comparison between various engines in service and in development demonstrated that the HiTME environmental requirements are realistic. Although there is significant variation in metalwork temperature, air temperature and air flow across applications and between potential mounting locations on a specific engine, given an electronic unit capable of operating reliably at these temperatures, suitable locations can be found, and scope exists to modify and tailor the environment using heat shields and cooling air flows. Further any hydromechanical component in a core location that utilises fuel or oil must limit the fuel/oil temperature to significantly less than 250 °C, and therefore provides additional mounting locations.
1.2 WP2 Concept Design
The concept design activity reviewed the available components and materials to assess the gaps between the current state of the art for high temperature electronics and the functionality envisaged to be implemented in the target environment. A gap analysis report (JTT114/0014) was issued.
A review of the currently available components and the potential capability of the Raytheon SiC CMOS process in conjunction with a variety of potential demonstrator applications led to the chosen design concept.
The chosen design concept is a multiplexing system for thermocouple measurements. The main drivers for the selection of this as a concept are…
• Potentially useful to near term engine designs for accuracy improvement.
• Potentially useful to near term engine designs for fault detection in future engine architectures.
• Makes use of very low leakage switches that can be implemented in SiC.
• Demonstrates functionally simple analogue and digital functionality in the SiC IC.
The benefits of such a block are analysed in more detail in the trade study JTT114/0001.
A concept design review was held and the minutes and review material are issued in report JTT114/0004. Specifications were produced for the SiC multiplexer ASIC (JTT114/0002) and for the complete electronics module (JTT114/0007).
Project timescales indicates early in the programme that integration and analysis of the electronics aspects of the design may be unacceptably delayed if they were implemented in a physically representative package (Representative from the aspects of mounting, mechanical integrity and interconnection to sensors and other sub-systems). The decision was made therefore to produce two separate demonstrator vehicles; Firstly an electrical demonstrator to evaluate the high temperature circuit function including the Raytheon SiC ASIC. Secondly a mechanical demonstrator of the physical integrity, mounting and interconnection of a small electronics LRU.
At the heart of the design is an 8 channel differential multiplexer (can be configured as 16 channel single ended) created from complimentary CMOS analogue switches (SiC).
A simple digital control section (State machine) controls the multiplexer switching to sequence through the multiplexer inputs in turn. In an additional part of the sequence the multiplexer output is forced out-of range high and to 0V differentially for longer periods.
The out of range period provides the receiving sub system with a marker to time acquisition of the data from the multiplexed channels (On the differential analogue output). During the zero phases, the IC auto zeros to remove offsets in the amplifier section. The amplifier section is implemented by four op-amps as a two stage differential amplifier. The amplifier gain is set by accurate resistors external to the IC and its gain is set to increase the thermocouple voltage range (Approx -2mV to +50mV) up to around 5V.
A bandgap reference is provided for the linear regulator (off chip) and to control reset of the logic elements. The design also provides two comparators, not required for the chosen function, but implemented as a useful building block for many other applications. In addition to the channels used for thermocouple measurement, two are dedicated to a Platinum Resistance Thermometer (PRT) for measurement of the thermocouple Cold Junction Compensation (CJC) temperature.
1.3 WP3 Electronic Design
The Electronic Design work package included: -
• Raytheon’s SiC ASIC
• Cissoid’s evaluation of their SOI ICs and silicon capacitors (from a third party)
• AEC Design of the electrical demonstrator module
The final electrical demonstrator design was subject to a detail design review with the consortium partners. The review also covered the other major work packages of the consortium parties and is minuted in report JTT114/0013.
1.3.1 SiC Multiplexer ASIC Design (RSL 6006)
Raytheon Systems Limited designed a part using their developmental SiC CMOS process. The RSL design is based on specification JTT114/0002 issued by AEC as deliverable D2.4 and provides the majority of the functionality in the demonstrator design.
Three batches were produced, the first suffering from leakage due to the need for design rules around feature spacing not previously encountered. Another batch provided valuable insight into the metal systems needed for reliable operation at temperature, reducing the effects of metal inter-diffusion. Raytheon report TR1554 summarises the key development activities of the ASIC and includes test data from probe testing
Conclusions from the RSL Workpackage included:-
• The RSL 6006 Functions as a multiplexer
• The Logic state machine has been shown to function
• The analogue performance, although functional, is compromised by SiC MOS transistor VT drift.
• The performance of the bandgap reference has not been shown due to unintended parasitic effects.
• A high temperature bond pad metallisation stack has been developed.
• Improvements to the process and design rules have been developed to improve circuit leakage
• The logic performance has been shown to be maintained for greater than 1180Hrs at 300°C continuous operation
1.3.2 Cissoid Component Evaluation
During the concept design phase, it was determined that SOI integrated circuits were already at a relatively high Technology Readiness Level (TRL) for operation up to 250°C, but confidence of operation at 300°C was lower. It was therefore decided not to include the parts in the demonstrator design, but evaluate a range of SOI parts for functional performance and life at the device level. This SOI device testing, plus testing of a range of silicon capacitors (Ipdia, France) formed the core of the Cissoid S.A. work package.
Cissoid’s testing has shown good performance and reliability of their parts. Some testing was unable to achieve 300°C and was limited to 270 °C due to test equipment or component limitations.
HT SOI component testing is reported in Cissoid report ‘HiTME Del 3.5’.
HT Silicon Capacitor testing is reported in Cissoid report ‘HiTME Del 3.7’.
1.3.3 Electrical Demonstrator Design
The detail of the electrical demonstrator was designed in conjunction with the multiplexer ASIC described in Section 2.3.1. Figure 2 5 shows the final circuit diagram, re-entered by API Technologies as subcontract manufacturers of the Electrical Demonstrator (also embedded below as a .pdf file). The SiC multiplexer ASIC is shown in the centre. Power for the IC is controlled by a discrete linear regulator circuit (below left). A resonator circuit provides a clock into the digital portion of the IC. Also included are the resistor networks (right) for setting the differential amplifier gain (right), input filter and protection components (left) and the PRT with its associated resistors (below).
Design and simulation of the HiTME demonstrator in a SPICE based simulator was generally successful on a number of levels.
It enabled the base design to be quickly captured using the inbuilt mixed-mode capability of SPICE. The parameters of the Raytheon SiC MOS process were then incorporated into the SPICE template components and this allowed circuits to be hierarchically designed, refined and understood as the project moved forward.
SPICE being a standard tool for integrated circuit design, provided a joint working environment between AEC and Raytheon which allowed us to discuss the design and points of key importance within a common framework. A Circuit Design Approval Meeting was held in accordance with AEC procedure to formally release the schematics for review and is minuted in JTT114/0012.
The SPICE software also provided a netliist export tool that enabled the design to be layed out at early stage to understand area and tracking constraints. Having such an end to end environment considerably reduced overall project risks.
The maturity of the Raytheon SiC CMOS process was lower than first anticipated, but the multiplexer chip did demonstrate many of the key electronic features required for a core mounted electronics module whilst highlighting the boundaries of SiC CMOS process. We now have a better understanding of the SiC CMOS process from an electronics perspective. Some of this understanding could be incorporated into the SPICE modelling environment but the issues surrounding the SiC oxide process should not be underestimated.
The final electronics design is documented in a functional description document JTT114/0011.
1.4 WP4 Mechanical Design
1.4.1 Thermal Scheme and Thermal Management Materials
TWI provided analysis of the thermal environment in a typical core engine location based on the output of work package 1. The report analyses the sources of heat into and within the unit and reviews the potential methods for managing that heat. These methods are summarised in Figure 2 6 and form the basis of a concept design for a bracket and heat shield to provide both alleviation for mechanical vibration and protection from heat radiated and conducted from the engine core.
The analysis is reported in “TWI Report for Project 20881 - December 2011”.
A specific study conducted by AEC analysed the effectiveness of thermoelectric cooling modules (JEN110/0002). This concluded that “The difference in temperature between the cold face and ambient of 16°C at the elevated temperature of 250˚C, where the device would be of greatest benefit, is however considered insufficient and does not merit the additional cost and power draw that the introduction of such cooling modules would incur”.
TWI provided analysis and test of the mechanical design solution of section 2.4.2 which is reported in 147DR.13. Delay to the actual mechanical demonstrator samples led to the testing being performed with a representative physical sample. The testing mapped the unit temperature as a function of bracket mounting temperature and air speed. A correlation between core temperature, air speed and sample temperature was shown and that at air speeds of around 0.6m/s the unit was close to the air temperature, and little affected by the core metalwork temperature.
1.4.2 Mechanical Demonstrator Design
The mechanical design challenge was to take existing microelectronics techniques and provide a package style which would be robust in a core engine environment including…
• Sustained High Temperature
• Temperature variation (Differential expansion)
• Vibration
• Trauma from engine servicing
• Contaminants and moisture
Key to this is the choice of connectorisation, necessary for easy maintenance by personnel. Various options for package and component substrate materials were evaluated. The design rationale, Design For Manufacture (DFM) and analysis of the package are reported in JTT114/0022.
The package is machined from Titanium, which has the benefit of low thermal coefficient of expansion and unlike Kovar, additional plating is not needed for environmental protection. The design allows the pins of the connector to pass through the substrate, enabling a number of methods of connection through to the substrate.
1.5 WP5 Material Selection
TWI undertook the majority of work package 5. The tests focused on the selection of die attach materials and wire bonding suitable for hermetic hybrid assemblies. The die attach materials investigated were all adhesives, both electrically conductive and non-conductive. Although some concern existed as to their longer term reliability at high temperatures, a number of new materials were available which showed promise and had suitable maximum working temperatures as specified by their manufacturers and can be processed by hybrid manufacturers using standard manufacturing processes.
The testing recommended that non-conductive adhesives should be used rather than conductive adhesive as they appear to be more robust. Also that cyanate ester based adhesives performed better than epoxy compounds for thermal storage. Although bond strength remained high after 500 hours at 300 °C, the bond strength was shown to weaken significantly as a result of thermal cycling (-55 to 250 °C).
Gold wire bonding to the gold pads of the RSL die, silicon capacitors and chip capacitors (Novacap, Kemet) was shown to provide a reliable connection as this maintains a mono-metallic electrical connection. Aluminium wire bonds to aluminium pads on the interposers and Semisouth die was shown to be robust during thermal storage but less reliable in thermal cycling.
The Ipdia silicon capacitors supplied performed better than expected despite the fact that the titanium-tungsten barrier layers between the gold and aluminium layers had been compromised. Evidence of this was seen as discoloration of the pads, believed to be a gold/aluminium intermetallic compound.
1.6 WP6 Manufacture
1.6.1 Electrical Demonstrators
The electrical demonstrators were packaged in commercially available 44 pin Kovar hermetic packages. The increased pin-out relative to the product concept of the mechanical demonstrator gave increased scope for testing. A thick film ceramic substrate was used providing connectivity on two layers. Printed resistors were used for high power applications where good accuracy was not needed. Cyanate-ester die attach adhesive was used as selected by work package 5. The transistor components were only available with an aluminium pad finish; therefore interposers (Aluminium clad molybdenum) were bonded to the gold substrate pads to give a mono-metallic wirebonding solution from the component to the interposer. The aluminium wire bonds would avoid known problems with the formation of gold-aluminium intermetallic compounds which would occur if the wire bond was made to the gold substrate .
1.6.2 Mechanical Demonstrators
The mechanical demonstrator design could not be easily produced by a single manufacturer as various capabilities were required.
• Machining and laser welding of Titanium
• Glass or ceramic to metal sealing of connector pins
• Microelectronics assembly
Although some companies approached could perform more than one of these, AEC selected Amphenol to produce the connectors, API Inc to provide the substrate and microelectronic assembly, and Walker Precision to machine the titanium package, substrate carrier, and to assemble the overall module. The routing for the assembly is included in Appendix E of JTT114/0022.
The connectors were supplied by Amphenol and were made with titanium shells so it matched the titanium package. A variety of glass materials to form the seal between the connector shell and connector pins were evaluated as the 300 °C upper temperature limit is beyond the expected capability of that for the standard product. The chosen materials appeared not to perform well, and project timescales required connectors to be delivered before these process issues could be resolved. The demonstrator hardware therefore does not provide the level of hermeticity required for reliability over life. The connector was considered good enough for the short duration of testing expected by this project however. Further connector development will be needed to realise a robust product for operational temperatures up to 300 °C.
The main titanium package was machined by Walker Precision who also laser welded the connectors into the package.
Thick film ceramic substrates were designed and manufactured by API Inc and supplied to Walker. These were ultrasonically soldered to a metal matrix (AlSiC) carrier plate using S-Bond 400 Alloy® (a high temperature zinc-silver-aluminium alloy) to give the substrate mechanical support and thermal transfer path to the package. This process was trialled and appeared effective; however the some of the final assemblies delaminated preventing their use. This process was understood to be a stop gap approach, as the design concept assumed Transient Liquid Phase (TLP) or Solid Liquid Inter Diffusion (SLID) soldering processes. Such an approach has showed significant promise in a parallel development funded by AEC (Ref HiTEN 2013, 8-10 July 2013 S5. The substrate and carrier plate are inserted into the package (Figure 2 11) and mechanically attached by five screws into a Spiraloc thread formed in the package which holds the torqued screw in the screw thread without the need of additional thread-lock compounds.
The assembly was then passed back to API to fit components to the substrate and gold wire bond components and connector pins to the substrate. Further development work is required on options for the pin connections. The chosen approach of wire bonding has the drawback of preventing easy rework and the need for special jigging for the wire-bonder to accommodate the protruding connectors to support and allow the substrate to be heated for the wire bonding process. This physical arrangement makes it a complicated process. Other design concepts were discussed but not adopted for the final demonstrator part. These may have merit, but include other challenges.
1 Use a solder material to join the pins to the substrate. Ultrasonic soldering trials with the S-bond 400 solder alloy showed poor wetting of the joint, so this approach was not used.
2 Use a mechanical interposer with sprung contacts. Concerns were raised about the mechanical tolerance between the two connectors causing stress on the connector glass to metal seals, and the likely loss of spring coefficient at high temperatures causing poor reliability. This approach is advantageous however as it allows the substrate to be assembled separately from the package and removed for rework.
The fully assembled body was returned to Walker Precision for the titanium package lid to be laser welded to the package in an inert atmosphere to form a hermetic assembly.
1.7 WP7 Test Methods
The overall project test strategy was set out in report JTT114/0006. This report details the top level testing intended across the programme.
Included in JTT114/0006 is testing planned to uprate other components, notably Vishay (Nice) resistor networks. This work was contracted to CALCE See WP8.
The detailed functional test requirements for the demonstrator (electrical) module are issued in JTT114/0009. This report defines the electrical tests required and the method used to connect to and accurately control the temperature of the circuit under test. The fixture shown in Figure 2 12 allows test access whilst heating the unit to 300 °C on the work bench, or can be placed inside a thermal chamber at up to 200 °C and be used to elevate the sample temperature beyond.
The demonstrator function outputs a sequence of varying voltages proportional to the multiplexed inputs. As these cannot be measured using a DC meter, and cannot be read accurately from an oscilloscope, a data acquisition system was developed to monitor the outputs (JTT114/0016). The monitoring system developed was based on a National Instruments USB-6351 controlled by NI LabVIEW Signal Express software©.
Testing was performed on a number of modules with mixed success. The reference voltage, known not to be functional was back driven externally. Although tests at chip level showed the analogue portions of the chip to be functional, not all could not be repeated in an assembled module. The comparators and multiplexers were functional, however the successes in testing the auto zeroing opamps could not be repeated in the assembled unit.
Some of the units were initially faulty, traced to a number of the Ipdia silicon capacitors being short circuit. As these were mostly for noise filtering, the affected components could be isolated by removal of the wire bond without adversely affecting the modules for experimental use. Of the three possible causes, ESD damage, mechanical damage and the incorrect use of a conductive die attach material, the latter is believed to be most likely as good ESD precautions were used during build, and no physical damage is apparent on the die.
Test strategy for the mechanical module was reported in JTT114/0021. Manufacturing delays with the demonstrator parts necessitated the simplification of planned testing. The testing performed is reported in JTT114/0023. During limited time at 300 °C no adverse effects were seen on the module.
Potential Impact:
Conclusions
The HiTME project provided a very challenging target to achieve TRL6 for a 300 °C capable electronics module, the key difficulties being…
• Low maturity of the SiC CMOS process.
• Very limited supply chain for electronic components specified beyond 200 °C.
• Back metallisation and pad metallisation not designed for high temperature operation, and difficulty in obtaining parts with non-standard finishes.
• Inherent reduction in accuracy and functional complexity achievable at high temperature precludes like-for-like comparison with MIL-STD temperature (-55/+125°C) functions.
• Inconsistency in back metallisation and pad metallisation on components making it necessary to use a range of die attach/interconnection methods. This makes for a complicated manufacturing process for the assembly.
The HiTME programme successfully…
• Mapped and defined the realistic operating conditions across the core engine environment
• Defined a concept for an achievable core mounted function with potential system benefits
• Advanced the state of the art in HT SiC CMOS integrated circuit design
• Increased understanding of the performance of HTSOI integrated circuits beyond 250 °C
• Realised two separate demonstrator vehicles focusing individually on electrical performance and mechanical integrity
• Demonstrated the potential for reliable operation in future designs
• Created a mechanical design concept which could be realistically deployed in a core engine environment subject to further process development
• Improved the knowledge of the best current adhesives and their limitations for use beyond 200°C
• Resolved many design-for-manufacture issues associated with high temperature modules for aerospace
• Highlighted the additional test duration that will be necessary to achieve confidence in operating life of parts, due to the small acceleration factor that is achievable and the lack of pedigree from a large installed base of similar units (compared to MIL-STD temp electronics)
• Integrated a consortium of companies and their wider supply chain in a project with strong interrelationships between each of the partner’s tasks
Various lessons were learned…
• The successful introduction of a high temperature product is inextricably linked with control of the supply chain
• Polymeric materials (eg die attach adhesives) are not suitable for long term use beyond 200 °C
• The OE cost of HT electronics is at least an order of magnitude higher than the equivalent function in a more benign (still harsh, e.g. fan-case) environment. Deployment must ‘buy itself’ onto the product through the enablement of other benefits (e.g. a sensor in a hot environment where local signal conditioning is absolutely necessary, which provides a SFC improvement)
• Statistical methods cannot be used meaningfully unless relatively large samples can be measured
• Components and their interconnecting metal systems need to be tailored to survive temperatures well beyond the planned operating temperature to provide margin by which reliability test times can be reduced without the introduction of alternative modes or physics of failure.
Dissemination
The project has been disseminated at various events throughout the project…
Cambridge Awards Week, 19-23 March 2012 TWI Opening Presentation; N. Stockham; TWI Limited
HITEC 2012 THP11 Digital and Analogue Integrated Circuits in Silicon Carbide for High Temperature Operations, Ewan Ramsey, Raytheon UK
NMI Harsh Environment Electronics, 23 Jan 2013 Presentation of mechanical demonstrator tests & thermal analysis, A Whitaker TWI.
HiTEN 2013, 8-10 July 2013 S3 Sensor Interface Applications for High Temperature Precision Amplifiers; Etienne Vanzieleghem, Pierre Delatte, David Baldwin, Jean-Chistophe Doucet; Cissoid S.A.
HiTEN 2013, 8-10 July 2013 S4 Uprating in the Development of a 250C Avionics Control System
Diganta Das, University of Maryland, College Park (F. Patrick McCluskey)
HiTEN 2013, 8-10 July 2013 S5 Solder and Die Attach for High Temperature Electronic Packaging
Patrick McCluskey, University of Maryland (C. Patel, H. Greve)
The prime aim of the HiTME project has been to develop a safety-critical electronic system which can operate reliability when installed in the severe engine core environment. Central to this objective, will be the development of electronic components and material technologies along with smart thermal and packaging designs that make the concept feasible.
In order to design a product capable of withstanding the high temperatures associated with an engine core installation, whilst still maintaining performance (accuracy) and life, fundamental advancement in key technological areas were necessary to investigate.
The following areas were seen as the underpinning building blocks to ‘enable’ a new generation product and that formed the core of the research activity.
• Component Enhancement (HTSOI, SiC & Passive Components)
• Thermal Design (Cooling Technologies)
• Material Selection (Material Technologies)
• Packaging / Installation Design (Novel Packaging)
• Develop Test Methods (and Analyses)
The work was apportioned in the consortium as follows:-
AEC - Management
Operational environment
Electronics and mechanical design
Test methods and analysis
Raytheon - Concept design
SiC CMOS integrated circuit design and manufacture
TWI limited - Materials Evaluation
- Thermal management solutions
Cissoid S.A. - SOI integrated circuit supply and characterisation
Passive component characterisation
Project Context and Objectives:
Introduction
To establish knowledge in key areas of high temperature electronics development, the project integrates the design, development and test of leading edge materials and electronic components with novel test methods. These activities, augmented by academic paper research, will deliver a combination of test vehicles to evaluate material technology, manufacturing process, and life expectancy of representative elements from an engine control system, capable of fulfilling today and tomorrow’s engine needs.
The goal of the research program was to design an engine control sub-system utilising, currently available, High Temperature Silicon-on-Insulator (“HTSOI”) and/or Silicon Carbide (“SiC”) components. Where components necessary for the development of key engine control functionality are not currently available or cannot effectively be thermally managed, bespoke SiC, Complementary Metal Oxide Semiconductor (“CMOS”) devices will be specifically designed and characterised by Raytheon Systems Limited (“RSL”).
The majority of civil ECUs are installed on the engine fan-case. While this location is certainly harsh with respect to vibration and temperature transients, it is unlikely that any electronic products designed today, for installation on the fan-case, would survive at the extreme temperatures generated by the engine core. There is therefore a significant gap between the future engine need and current state-of-the-art when viewed at the ECU product level.
However, for many of the research objectives defined, progress beyond the current state-of-the-art, in that particular discipline, is anticipated. The individual advances in these key technological areas will be combined and integrated to develop a new generation ECS which will, itself, progress beyond the current ECU capability.
Therefore, in order to design a product capable of withstanding the high temperatures associated with an engine core installation, whilst still maintaining similar performance (accuracy) and life, fundamental advancement in key technological areas will be necessary. The following areas are seen as the underpinning building blocks that will enable a new generation product.
• Component enhancement (HTSOI, SiC & passive components)
• Thermal design (cooling technologies)
• Material selection (material technologies)
• Packaging / installation design (novel packaging)
• Develop test methods (and analyses)
Component Enhancement
Electronic component technology exists today, which is capable of operation to 2250C, albeit with a short life, not consistent with aerospace maintenance practice. Cissoid is a major player in the high temperature electronics market, having developed a range of components using a HTSOI process. A number of these components are of use to an engine control system designer, but many key component types are currently unavailable.
There is also a limited, but expanding, market of electronic components, based upon SiC technology, which can operate successfully to temperatures in excess of 300 Deg C for periods of time consistent with aircraft maintenance practices. Unfortunately, the functionality afforded by this technology is yet to move beyond basic switching components for high power application. Through a number of prior research programmes, RSL has developed a SiC CMOS process capable of >300 Deg C operation. This provides an opportunity to develop more complex components, such as sensor amplifiers, currently unavailable in SiC technology.
Degradation in the performance of passive components at elevated temperature is well understood from basic physics. Capacitors, in particular, exhibit poor charge retention at high temperature which results in a very large de-rating at the circuit design level, which ultimately leads to much larger large components. Cissoid has experience with a new technology of capacitors which show reliable performance at elevated temperatures.
Thus, in the area of component enhancement, the challenge for the project was three-fold:
• To develop a system design using component parts which are not rated to operate at extreme temperatures, by a combination of parameter de-rating and active thermal design. This work will be carried out in work packages 3.4 and 4.1 circuit block development’ and ‘evaluate thermal management solutions’.
• To rigorously examine the HTSOI process to understand the constraints and failure mechanisms associated with operation beyond current rated temperatures. This activity will include component characterisation and qualification and will be carried out in work package 3.2; further detail is provided below.
• To evaluate and characterise component technologies which can operate at the required temperatures. Two separate component technology development activities will be carried out as part of this program. SiC CMOS integrated circuits will be developed as part of work package 3.1. Temperature capable chip capacitors will be characterised as part of work package 3.3; further detail is provided below.
Characterisation and Qualification of HTSOI Components
Testing previously performed by Cissoid appears to indicate that the potential of HTSOI technology is yet to be fully exploited. Tests carried out to date confirm that HTSOI based circuits can operate at 250ºC and survive excursions up to 375ºC. However, these components have not been fully characterised and qualified for operation at the temperatures applicable to core engine electronics. It is the prime goal of Cissoid to develop the required know-how to develop the test methods and vehicles necessary for this qualification. An important element in the qualification process will be a rigorous examination of HTSOI components to understand the constraints and failure mechanisms associated with operation beyond the rated temperatures. Once a characterisation / qualification method has been established, it may then be used to validate the performance of other electronic components such as passive components. The final objective is to establish characterisation at component level for use by the system designer, to optimise performance and efficiency of a complete sub-system, at the design stage.
Development of SiC Components
RSL has already demonstrated state of the art through the development of n and p type FET transistors on SiC which have been tested up to 350 Deg C (Reference Clark et al, ECSCRM Oslo, Aug 31 2010). A simple ring oscillator integrated circuit (900 transistors) has also been demonstrated at 300 Deg C. Work continues to develop an even higher temperature capable process. The benefits of such a high temperature process are three-fold:
• The ability to offer active electronics solutions in extreme environments [>300 Deg C]
• The ability to accelerate life test on active electronics for lower temp operation [200 to 300 Deg C]
• The possibility to offer extended life electronics over current state of the art at 225 Deg C.
Existing silicon based state of the art from commercially available semiconductor processes provides junction temperatures up to 2250C (Reference: X-Fab 1u HT SOI process). There has been research into the use of other semiconductor materials for high temperature applications including GaN, GaAs and Diamond. These do not hold out so much promise, or are significantly less mature than the SiC CMOS demonstrated by RSL. Other SiC based state of the art includes lower capability NMOS and JFET based research presented recently by NASA, General Electric and Bosch groups.
High Temperature Characterisation of Chip Capacitors
New technology capacitors with very interesting properties at high temperature have been recently identified by Cissoid. These capacitors are thought to have a close match to active HTSOI devices and are therefore expected to benefit from extended temperature stability.
When compared with ceramic chip capacitors, typically used for high temperature applications, these components offers high temperature stability, lower leakage, higher density and potentially a very good reliability. The selection and validation of packaging techniques suitable for operation at high temperatures will be the key element of this activity.
Thermal Design
Thermal management has become a significant issue in recent generations of ECUs and for future systems this will likely become a product differentiator; there are two key considerations;
• Rising density, clock speeds and power of electronic components, leading to increasing demands for dissipation of the waste heat generated (Internal Source)
• Increased application of electronics to harsh temperature environments. (External Source)
If thermal management design is inadequate, premature component failure can be expected wither by direct failure of the semiconductor or, more likely, by progressive accumulation of thermo-mechanical damage and eventual cracking of the interconnect structures. To date industry have developed solutions based on new materials for heat-sinks and heat spreaders, interface materials or joints for thermally efficient assembly of components. While these solutions have allowed an extension of the range of passive cooling, an increasing demand in aerospace applications has driven the development of new active cooling systems, which have ramifications in terms of cost, complexity and reliability.
This project has tried to address the total thermal management system: junction through to die to package to board/substrate to enclosure to external environment. Novel cooling and insulation approaches and assessment of the feasibility of using SMART electronics to protect more sensitive components and reduce internal heat generation at key times have been examined in the project.
TWI and Aero Engine Controls have extensive experience in both the thermal management in current aerospace engine control products and the technologies used in other sectors such as automotive, computer and oil & gas. TWI is also developing novel textured heat exchange surfaces, heat-sink systems and spray coated thermally conducting/insulating interface materials which will be assessed for this application.
Material Selection
Conventional consumer electronics operate at temperatures in the range 0 - 70°C. This enables extensive use of polymer based attachment and encapsulation systems, printed circuit board technology and solder package attachment systems. These materials, packaging and production assembly processes have been refined over the last 30 years and have resulted in relatively high reliability products for their operational/design life which may be only 2 - 5 years.
These techniques, together with the more expensive ceramic, glass and metal housed ‘high reliability systems’ have been developed for sectors, such as aerospace, to operate at ambient temperatures of 125°C for significantly longer periods of time (e.g.20 years). However, above these temperatures there are significant concerns as to the performance of these materials and their associated interconnect systems, for example:
To operate at ambient temperatures of 250°C with transients up to 300°C this project will implement a step change in package material and interconnect technologies.
Success will be achieved by establishing combinations of materials and interconnect systems that are compatible metallurgically, chemically, mechanically and electrically, while subjected to an engine core environment.
Packaging and Installation Design
Currently ECU’s are mounted on the engine fancase, isolated from engine vibration by the use of elastometric anti-vibration (“AV”) mounts. When moving closer to the engine core (i.e. higher operating temperature environments) these materials are no longer suitable but there are all-metal solutions which have been used in aerospace and off-shore oil/gas applications which may be suitable at increased temperatures. An alternative approach has been consideered, made feasible by the reduction in size and weight of a disbursed node ECU, is to hard-mount the ECU directly to the engine metalwork.
Disbursed nodes could either be in the form of an autonomous line replaceable unit (see adjacent picture) or form part of a ‘smart’ hydro-mechanical system (see picture below). The latter involves more complex integration activities but may provide a simpler and cheaper solution to the end customer.
In each case it was important to consider external interconnect (harnessing and connectors), mounting and the provision of a good grounding path for electro magnetic compatability (“EMC”) and lightning strike threats. Conventional ECU external connectors are capable of 260°C but tend to be large and heavy designs.
For high temperature micro-electronic packages, smaller connectors such as micro-D or nano, might be better suited to keep to size and weight of the unit down. Interconnect can be made via direct wire bond on substrate or high temperature printed circuit board (PCB) connectors with flex or wire.
Selecting the right materials is key to packaging design. Normally aluminium would be selected for its light weight and high thermal conductivity, but at elevated temperatures the material properties (e.g. strength) will be affected; this may see a move more towards steel, kovar or titanium. It is important to understand and consider how all the materials that makes up an assembly, react to each (e.g. thermal expansion matching and galvanic corrosion).
Environmental protection is another factor to consider in the packaging design; traditionally fluorosilicone (fuel resistant) seals would be used to restrict fluid ingress and sand/dust. The trend for micro-electronics is to make the design hermetic; this results in a cleaner (and potentially more reliable) internal environment, but at an additional cost.
Statistical Validation of Life Test Methods
Testing is a critical issue for this development as the requirements will stretch the operating conditions well beyond conventional limits, especially for resilience to temperature and vibration, such that established data cannot be used and additional new test techniques will be required.
In particular, lifetime assessment is usually based on extrapolation of data from tests performed under conditions of accelerated stress, especially for temperature and temperature cycling range. So this presents a challenge for acceleration of tests for high operating temperatures – as there is a risk of moving into regimes of unrepresentative failure modes. Additional tests will be required to establish changes in material structures and properties at critical interfaces which will be essential to map out safe operating conditions and employ physics of failure principles – data on bulk properties are inadequate for this characterisation.
Improvements are also required in the time taken to achieve results during development. Even with highly accelerated stress acceleration, conventional reliability testing such a thermal cycling can take many thousands of hours to perform and then only produce a pass/fail result of limited value. Test techniques are required which produce measurements in real time such that degradation trends are identified early rather than just failure points, and test times can be reduced. The following were considered:-
• Precision reliability testing employs real-time electrical parameter measurement to identify degradation trends during a thermal cycling regime which is controlled with high precision to improve the scatter in results for more precise and faster predictions of lifetime
• Electro migration testing combines thermal and voltage stresses to identify the physical and electrical stability of conductors and dielectrics for both semiconductor components and interconnect substrates – a known problem for high temperature electronics.
• Nano-indentation is a high precision technique for determining the elastic and plastic characteristics of materials which have been subjected thermo-mechanical stresses and are in the process of degradation. This technique is especially appropriate for joints and provides essential input into physics of failure maps and lifetime prediction e.g. creep and fatigue resistance.
• As material properties change at elevated temperatures, combinational testing is very important. Vibration at temperature is an essential test technique for overall assemblies but needs refinement and application to identify critical resonant frequency responses at temperature for key components such as micro interconnect in cavity packages.
• Neural network test data acquisition is one possible technique for rapid collection and assimilation of data in real-time which may significantly enhance capability and reduce test times.
Project Results:
1 Introduction
The prime aim of the HiTME project is to develop a safety-critical electronic system which can operate reliability when installed in the severe engine core environment. Central to this objective, will be the development of electronic components and material technologies along with smart thermal and packaging designs that make the concept feasible.
In order to design a product capable of withstanding the high temperatures associated with an engine core installation, whilst still maintaining performance (accuracy) and life, fundamental advancement in key technological areas are necessary.
The following areas were seen as the underpinning building blocks to ‘enable’ a new generation product and that formed the core of the research activity.
• Component Enhancement (HTSOI, SiC & Passive Components)
• Thermal Design (Cooling Technologies)
• Material Selection (Material Technologies)
• Packaging / Installation Design (Novel Packaging)
• Develop Test Methods (and Analyses)
These tasks were set out in the work package descriptions of “JTI-CS-2010-4-SAGE-03-05” and the work carried out in response to the Description of Work is summarised in this report. The work was apportioned between AEC and the other partners in the HiTME consortium as follows…
AEC - Management
Operational environment
Electronics and mechanical design
Test methods and analysis
Raytheon - Concept design
SiC CMOS integrated circuit design and manufacture
TWI limited - Materials Evaluation
- Thermal management solutions
Cissoid S.A. - SOI integrated circuit supply and characterisation
Passive component characterisation
1 Work Package Descriptions and Work Undertaken
1.1 WP1 Operational Environment
This work package (WP) defined the environment within which the electronic unit, parts and processes were specified to operate. This included the temperature and vibration environment at various locations within the core mounted accessories zone(s) of the engine. Further definition was made in relation to the chosen function for demonstration derived from WP2 Concept Design.
The environment definition was reported in subsequent issues of report JTT114/0003. The HiTME programme [JTI-CS-2010-4-SAGE-03-05] defines the operating environment for any core mounted system as having a maximum steady state temperature of 250˚C with transient excursions to 300˚C. The analysis of PSRD data and comparison between various engines in service and in development demonstrated that the HiTME environmental requirements are realistic. Although there is significant variation in metalwork temperature, air temperature and air flow across applications and between potential mounting locations on a specific engine, given an electronic unit capable of operating reliably at these temperatures, suitable locations can be found, and scope exists to modify and tailor the environment using heat shields and cooling air flows. Further any hydromechanical component in a core location that utilises fuel or oil must limit the fuel/oil temperature to significantly less than 250 °C, and therefore provides additional mounting locations.
1.2 WP2 Concept Design
The concept design activity reviewed the available components and materials to assess the gaps between the current state of the art for high temperature electronics and the functionality envisaged to be implemented in the target environment. A gap analysis report (JTT114/0014) was issued.
A review of the currently available components and the potential capability of the Raytheon SiC CMOS process in conjunction with a variety of potential demonstrator applications led to the chosen design concept.
The chosen design concept is a multiplexing system for thermocouple measurements. The main drivers for the selection of this as a concept are…
• Potentially useful to near term engine designs for accuracy improvement.
• Potentially useful to near term engine designs for fault detection in future engine architectures.
• Makes use of very low leakage switches that can be implemented in SiC.
• Demonstrates functionally simple analogue and digital functionality in the SiC IC.
The benefits of such a block are analysed in more detail in the trade study JTT114/0001.
A concept design review was held and the minutes and review material are issued in report JTT114/0004. Specifications were produced for the SiC multiplexer ASIC (JTT114/0002) and for the complete electronics module (JTT114/0007).
Project timescales indicates early in the programme that integration and analysis of the electronics aspects of the design may be unacceptably delayed if they were implemented in a physically representative package (Representative from the aspects of mounting, mechanical integrity and interconnection to sensors and other sub-systems). The decision was made therefore to produce two separate demonstrator vehicles; Firstly an electrical demonstrator to evaluate the high temperature circuit function including the Raytheon SiC ASIC. Secondly a mechanical demonstrator of the physical integrity, mounting and interconnection of a small electronics LRU.
At the heart of the design is an 8 channel differential multiplexer (can be configured as 16 channel single ended) created from complimentary CMOS analogue switches (SiC).
A simple digital control section (State machine) controls the multiplexer switching to sequence through the multiplexer inputs in turn. In an additional part of the sequence the multiplexer output is forced out-of range high and to 0V differentially for longer periods.
The out of range period provides the receiving sub system with a marker to time acquisition of the data from the multiplexed channels (On the differential analogue output). During the zero phases, the IC auto zeros to remove offsets in the amplifier section. The amplifier section is implemented by four op-amps as a two stage differential amplifier. The amplifier gain is set by accurate resistors external to the IC and its gain is set to increase the thermocouple voltage range (Approx -2mV to +50mV) up to around 5V.
A bandgap reference is provided for the linear regulator (off chip) and to control reset of the logic elements. The design also provides two comparators, not required for the chosen function, but implemented as a useful building block for many other applications. In addition to the channels used for thermocouple measurement, two are dedicated to a Platinum Resistance Thermometer (PRT) for measurement of the thermocouple Cold Junction Compensation (CJC) temperature.
1.3 WP3 Electronic Design
The Electronic Design work package included: -
• Raytheon’s SiC ASIC
• Cissoid’s evaluation of their SOI ICs and silicon capacitors (from a third party)
• AEC Design of the electrical demonstrator module
The final electrical demonstrator design was subject to a detail design review with the consortium partners. The review also covered the other major work packages of the consortium parties and is minuted in report JTT114/0013.
1.3.1 SiC Multiplexer ASIC Design (RSL 6006)
Raytheon Systems Limited designed a part using their developmental SiC CMOS process. The RSL design is based on specification JTT114/0002 issued by AEC as deliverable D2.4 and provides the majority of the functionality in the demonstrator design.
Three batches were produced, the first suffering from leakage due to the need for design rules around feature spacing not previously encountered. Another batch provided valuable insight into the metal systems needed for reliable operation at temperature, reducing the effects of metal inter-diffusion. Raytheon report TR1554 summarises the key development activities of the ASIC and includes test data from probe testing
Conclusions from the RSL Workpackage included:-
• The RSL 6006 Functions as a multiplexer
• The Logic state machine has been shown to function
• The analogue performance, although functional, is compromised by SiC MOS transistor VT drift.
• The performance of the bandgap reference has not been shown due to unintended parasitic effects.
• A high temperature bond pad metallisation stack has been developed.
• Improvements to the process and design rules have been developed to improve circuit leakage
• The logic performance has been shown to be maintained for greater than 1180Hrs at 300°C continuous operation
1.3.2 Cissoid Component Evaluation
During the concept design phase, it was determined that SOI integrated circuits were already at a relatively high Technology Readiness Level (TRL) for operation up to 250°C, but confidence of operation at 300°C was lower. It was therefore decided not to include the parts in the demonstrator design, but evaluate a range of SOI parts for functional performance and life at the device level. This SOI device testing, plus testing of a range of silicon capacitors (Ipdia, France) formed the core of the Cissoid S.A. work package.
Cissoid’s testing has shown good performance and reliability of their parts. Some testing was unable to achieve 300°C and was limited to 270 °C due to test equipment or component limitations.
HT SOI component testing is reported in Cissoid report ‘HiTME Del 3.5’.
HT Silicon Capacitor testing is reported in Cissoid report ‘HiTME Del 3.7’.
1.3.3 Electrical Demonstrator Design
The detail of the electrical demonstrator was designed in conjunction with the multiplexer ASIC described in Section 2.3.1. Figure 2 5 shows the final circuit diagram, re-entered by API Technologies as subcontract manufacturers of the Electrical Demonstrator (also embedded below as a .pdf file). The SiC multiplexer ASIC is shown in the centre. Power for the IC is controlled by a discrete linear regulator circuit (below left). A resonator circuit provides a clock into the digital portion of the IC. Also included are the resistor networks (right) for setting the differential amplifier gain (right), input filter and protection components (left) and the PRT with its associated resistors (below).
Design and simulation of the HiTME demonstrator in a SPICE based simulator was generally successful on a number of levels.
It enabled the base design to be quickly captured using the inbuilt mixed-mode capability of SPICE. The parameters of the Raytheon SiC MOS process were then incorporated into the SPICE template components and this allowed circuits to be hierarchically designed, refined and understood as the project moved forward.
SPICE being a standard tool for integrated circuit design, provided a joint working environment between AEC and Raytheon which allowed us to discuss the design and points of key importance within a common framework. A Circuit Design Approval Meeting was held in accordance with AEC procedure to formally release the schematics for review and is minuted in JTT114/0012.
The SPICE software also provided a netliist export tool that enabled the design to be layed out at early stage to understand area and tracking constraints. Having such an end to end environment considerably reduced overall project risks.
The maturity of the Raytheon SiC CMOS process was lower than first anticipated, but the multiplexer chip did demonstrate many of the key electronic features required for a core mounted electronics module whilst highlighting the boundaries of SiC CMOS process. We now have a better understanding of the SiC CMOS process from an electronics perspective. Some of this understanding could be incorporated into the SPICE modelling environment but the issues surrounding the SiC oxide process should not be underestimated.
The final electronics design is documented in a functional description document JTT114/0011.
1.4 WP4 Mechanical Design
1.4.1 Thermal Scheme and Thermal Management Materials
TWI provided analysis of the thermal environment in a typical core engine location based on the output of work package 1. The report analyses the sources of heat into and within the unit and reviews the potential methods for managing that heat. These methods are summarised in Figure 2 6 and form the basis of a concept design for a bracket and heat shield to provide both alleviation for mechanical vibration and protection from heat radiated and conducted from the engine core.
The analysis is reported in “TWI Report for Project 20881 - December 2011”.
A specific study conducted by AEC analysed the effectiveness of thermoelectric cooling modules (JEN110/0002). This concluded that “The difference in temperature between the cold face and ambient of 16°C at the elevated temperature of 250˚C, where the device would be of greatest benefit, is however considered insufficient and does not merit the additional cost and power draw that the introduction of such cooling modules would incur”.
TWI provided analysis and test of the mechanical design solution of section 2.4.2 which is reported in 147DR.13. Delay to the actual mechanical demonstrator samples led to the testing being performed with a representative physical sample. The testing mapped the unit temperature as a function of bracket mounting temperature and air speed. A correlation between core temperature, air speed and sample temperature was shown and that at air speeds of around 0.6m/s the unit was close to the air temperature, and little affected by the core metalwork temperature.
1.4.2 Mechanical Demonstrator Design
The mechanical design challenge was to take existing microelectronics techniques and provide a package style which would be robust in a core engine environment including…
• Sustained High Temperature
• Temperature variation (Differential expansion)
• Vibration
• Trauma from engine servicing
• Contaminants and moisture
Key to this is the choice of connectorisation, necessary for easy maintenance by personnel. Various options for package and component substrate materials were evaluated. The design rationale, Design For Manufacture (DFM) and analysis of the package are reported in JTT114/0022.
The package is machined from Titanium, which has the benefit of low thermal coefficient of expansion and unlike Kovar, additional plating is not needed for environmental protection. The design allows the pins of the connector to pass through the substrate, enabling a number of methods of connection through to the substrate.
1.5 WP5 Material Selection
TWI undertook the majority of work package 5. The tests focused on the selection of die attach materials and wire bonding suitable for hermetic hybrid assemblies. The die attach materials investigated were all adhesives, both electrically conductive and non-conductive. Although some concern existed as to their longer term reliability at high temperatures, a number of new materials were available which showed promise and had suitable maximum working temperatures as specified by their manufacturers and can be processed by hybrid manufacturers using standard manufacturing processes.
The testing recommended that non-conductive adhesives should be used rather than conductive adhesive as they appear to be more robust. Also that cyanate ester based adhesives performed better than epoxy compounds for thermal storage. Although bond strength remained high after 500 hours at 300 °C, the bond strength was shown to weaken significantly as a result of thermal cycling (-55 to 250 °C).
Gold wire bonding to the gold pads of the RSL die, silicon capacitors and chip capacitors (Novacap, Kemet) was shown to provide a reliable connection as this maintains a mono-metallic electrical connection. Aluminium wire bonds to aluminium pads on the interposers and Semisouth die was shown to be robust during thermal storage but less reliable in thermal cycling.
The Ipdia silicon capacitors supplied performed better than expected despite the fact that the titanium-tungsten barrier layers between the gold and aluminium layers had been compromised. Evidence of this was seen as discoloration of the pads, believed to be a gold/aluminium intermetallic compound.
1.6 WP6 Manufacture
1.6.1 Electrical Demonstrators
The electrical demonstrators were packaged in commercially available 44 pin Kovar hermetic packages. The increased pin-out relative to the product concept of the mechanical demonstrator gave increased scope for testing. A thick film ceramic substrate was used providing connectivity on two layers. Printed resistors were used for high power applications where good accuracy was not needed. Cyanate-ester die attach adhesive was used as selected by work package 5. The transistor components were only available with an aluminium pad finish; therefore interposers (Aluminium clad molybdenum) were bonded to the gold substrate pads to give a mono-metallic wirebonding solution from the component to the interposer. The aluminium wire bonds would avoid known problems with the formation of gold-aluminium intermetallic compounds which would occur if the wire bond was made to the gold substrate .
1.6.2 Mechanical Demonstrators
The mechanical demonstrator design could not be easily produced by a single manufacturer as various capabilities were required.
• Machining and laser welding of Titanium
• Glass or ceramic to metal sealing of connector pins
• Microelectronics assembly
Although some companies approached could perform more than one of these, AEC selected Amphenol to produce the connectors, API Inc to provide the substrate and microelectronic assembly, and Walker Precision to machine the titanium package, substrate carrier, and to assemble the overall module. The routing for the assembly is included in Appendix E of JTT114/0022.
The connectors were supplied by Amphenol and were made with titanium shells so it matched the titanium package. A variety of glass materials to form the seal between the connector shell and connector pins were evaluated as the 300 °C upper temperature limit is beyond the expected capability of that for the standard product. The chosen materials appeared not to perform well, and project timescales required connectors to be delivered before these process issues could be resolved. The demonstrator hardware therefore does not provide the level of hermeticity required for reliability over life. The connector was considered good enough for the short duration of testing expected by this project however. Further connector development will be needed to realise a robust product for operational temperatures up to 300 °C.
The main titanium package was machined by Walker Precision who also laser welded the connectors into the package.
Thick film ceramic substrates were designed and manufactured by API Inc and supplied to Walker. These were ultrasonically soldered to a metal matrix (AlSiC) carrier plate using S-Bond 400 Alloy® (a high temperature zinc-silver-aluminium alloy) to give the substrate mechanical support and thermal transfer path to the package. This process was trialled and appeared effective; however the some of the final assemblies delaminated preventing their use. This process was understood to be a stop gap approach, as the design concept assumed Transient Liquid Phase (TLP) or Solid Liquid Inter Diffusion (SLID) soldering processes. Such an approach has showed significant promise in a parallel development funded by AEC (Ref HiTEN 2013, 8-10 July 2013 S5. The substrate and carrier plate are inserted into the package (Figure 2 11) and mechanically attached by five screws into a Spiraloc thread formed in the package which holds the torqued screw in the screw thread without the need of additional thread-lock compounds.
The assembly was then passed back to API to fit components to the substrate and gold wire bond components and connector pins to the substrate. Further development work is required on options for the pin connections. The chosen approach of wire bonding has the drawback of preventing easy rework and the need for special jigging for the wire-bonder to accommodate the protruding connectors to support and allow the substrate to be heated for the wire bonding process. This physical arrangement makes it a complicated process. Other design concepts were discussed but not adopted for the final demonstrator part. These may have merit, but include other challenges.
1 Use a solder material to join the pins to the substrate. Ultrasonic soldering trials with the S-bond 400 solder alloy showed poor wetting of the joint, so this approach was not used.
2 Use a mechanical interposer with sprung contacts. Concerns were raised about the mechanical tolerance between the two connectors causing stress on the connector glass to metal seals, and the likely loss of spring coefficient at high temperatures causing poor reliability. This approach is advantageous however as it allows the substrate to be assembled separately from the package and removed for rework.
The fully assembled body was returned to Walker Precision for the titanium package lid to be laser welded to the package in an inert atmosphere to form a hermetic assembly.
1.7 WP7 Test Methods
The overall project test strategy was set out in report JTT114/0006. This report details the top level testing intended across the programme.
Included in JTT114/0006 is testing planned to uprate other components, notably Vishay (Nice) resistor networks. This work was contracted to CALCE See WP8.
The detailed functional test requirements for the demonstrator (electrical) module are issued in JTT114/0009. This report defines the electrical tests required and the method used to connect to and accurately control the temperature of the circuit under test. The fixture shown in Figure 2 12 allows test access whilst heating the unit to 300 °C on the work bench, or can be placed inside a thermal chamber at up to 200 °C and be used to elevate the sample temperature beyond.
The demonstrator function outputs a sequence of varying voltages proportional to the multiplexed inputs. As these cannot be measured using a DC meter, and cannot be read accurately from an oscilloscope, a data acquisition system was developed to monitor the outputs (JTT114/0016). The monitoring system developed was based on a National Instruments USB-6351 controlled by NI LabVIEW Signal Express software©.
Testing was performed on a number of modules with mixed success. The reference voltage, known not to be functional was back driven externally. Although tests at chip level showed the analogue portions of the chip to be functional, not all could not be repeated in an assembled module. The comparators and multiplexers were functional, however the successes in testing the auto zeroing opamps could not be repeated in the assembled unit.
Some of the units were initially faulty, traced to a number of the Ipdia silicon capacitors being short circuit. As these were mostly for noise filtering, the affected components could be isolated by removal of the wire bond without adversely affecting the modules for experimental use. Of the three possible causes, ESD damage, mechanical damage and the incorrect use of a conductive die attach material, the latter is believed to be most likely as good ESD precautions were used during build, and no physical damage is apparent on the die.
Test strategy for the mechanical module was reported in JTT114/0021. Manufacturing delays with the demonstrator parts necessitated the simplification of planned testing. The testing performed is reported in JTT114/0023. During limited time at 300 °C no adverse effects were seen on the module.
Potential Impact:
Conclusions
The HiTME project provided a very challenging target to achieve TRL6 for a 300 °C capable electronics module, the key difficulties being…
• Low maturity of the SiC CMOS process.
• Very limited supply chain for electronic components specified beyond 200 °C.
• Back metallisation and pad metallisation not designed for high temperature operation, and difficulty in obtaining parts with non-standard finishes.
• Inherent reduction in accuracy and functional complexity achievable at high temperature precludes like-for-like comparison with MIL-STD temperature (-55/+125°C) functions.
• Inconsistency in back metallisation and pad metallisation on components making it necessary to use a range of die attach/interconnection methods. This makes for a complicated manufacturing process for the assembly.
The HiTME programme successfully…
• Mapped and defined the realistic operating conditions across the core engine environment
• Defined a concept for an achievable core mounted function with potential system benefits
• Advanced the state of the art in HT SiC CMOS integrated circuit design
• Increased understanding of the performance of HTSOI integrated circuits beyond 250 °C
• Realised two separate demonstrator vehicles focusing individually on electrical performance and mechanical integrity
• Demonstrated the potential for reliable operation in future designs
• Created a mechanical design concept which could be realistically deployed in a core engine environment subject to further process development
• Improved the knowledge of the best current adhesives and their limitations for use beyond 200°C
• Resolved many design-for-manufacture issues associated with high temperature modules for aerospace
• Highlighted the additional test duration that will be necessary to achieve confidence in operating life of parts, due to the small acceleration factor that is achievable and the lack of pedigree from a large installed base of similar units (compared to MIL-STD temp electronics)
• Integrated a consortium of companies and their wider supply chain in a project with strong interrelationships between each of the partner’s tasks
Various lessons were learned…
• The successful introduction of a high temperature product is inextricably linked with control of the supply chain
• Polymeric materials (eg die attach adhesives) are not suitable for long term use beyond 200 °C
• The OE cost of HT electronics is at least an order of magnitude higher than the equivalent function in a more benign (still harsh, e.g. fan-case) environment. Deployment must ‘buy itself’ onto the product through the enablement of other benefits (e.g. a sensor in a hot environment where local signal conditioning is absolutely necessary, which provides a SFC improvement)
• Statistical methods cannot be used meaningfully unless relatively large samples can be measured
• Components and their interconnecting metal systems need to be tailored to survive temperatures well beyond the planned operating temperature to provide margin by which reliability test times can be reduced without the introduction of alternative modes or physics of failure.
Dissemination
The project has been disseminated at various events throughout the project…
Cambridge Awards Week, 19-23 March 2012 TWI Opening Presentation; N. Stockham; TWI Limited
HITEC 2012 THP11 Digital and Analogue Integrated Circuits in Silicon Carbide for High Temperature Operations, Ewan Ramsey, Raytheon UK
NMI Harsh Environment Electronics, 23 Jan 2013 Presentation of mechanical demonstrator tests & thermal analysis, A Whitaker TWI.
HiTEN 2013, 8-10 July 2013 S3 Sensor Interface Applications for High Temperature Precision Amplifiers; Etienne Vanzieleghem, Pierre Delatte, David Baldwin, Jean-Chistophe Doucet; Cissoid S.A.
HiTEN 2013, 8-10 July 2013 S4 Uprating in the Development of a 250C Avionics Control System
Diganta Das, University of Maryland, College Park (F. Patrick McCluskey)
HiTEN 2013, 8-10 July 2013 S5 Solder and Die Attach for High Temperature Electronic Packaging
Patrick McCluskey, University of Maryland (C. Patel, H. Greve)
