Final Activity Report Summary - CHASP (Channel Modelling and Advanced Signal Processing for Wireless Communication Systems)
In this project we had two underlying fundamental studies. The first part dealt with the theoretical analysis and mathematical modelling of the phenomenon that occur in mobile / wireless / broadcast systems such as signal fading, shadowing loss and path loss. All these effects cause some kind of a power loss or quality of service degradation or total loss of connectivity which is also known as outage, and also these effects shape the coverage of the transmitted signal. We then attempted to model these effects using random processes theory and we came up with a simple model to effectively generate a fading process that would simulate the signal fading that occurs in wireless communications.
We showed that this method achieves the lowest computational complexity and is very suitable for hardware implementations. At this juncture we worked on the hardware implementation of the new method that we developed. The aim of the hardware implementation using commercially available tools is to show the applicability of our algorithm for a laboratory prototype for wireless channel simulators. We showed that our method achieves the lowest complexity, and we also showed that other existing more complex methods diverged numerically under quantisation effects, and hence those more well-known methods are not suitable for hardware implementation. We extended our work to cover fault tolerance under hardware implementation. We studied how we can achieve fault tolerance with FPGA implementation.
We showed that this method achieves the lowest computational complexity and is very suitable for hardware implementations. At this juncture we worked on the hardware implementation of the new method that we developed. The aim of the hardware implementation using commercially available tools is to show the applicability of our algorithm for a laboratory prototype for wireless channel simulators. We showed that our method achieves the lowest complexity, and we also showed that other existing more complex methods diverged numerically under quantisation effects, and hence those more well-known methods are not suitable for hardware implementation. We extended our work to cover fault tolerance under hardware implementation. We studied how we can achieve fault tolerance with FPGA implementation.