Objective The objective of FORMAT is to reduce the design time for complex hardware modules by providing a set of system-level methods and design tools supporting an enhanced version of VHDL. Emphasis will be placed on formal verification and synthesis methods, whose introduction is expected to lead not only to designs of greater reliability but also to earlier recognition of errors in the design cycle. A transformation approach will also be explored.FORMAT will specify and develop a graphical front-end and a specification language (VHDL-S) for use by designers. The graphical interface will use timing diagrams augmented to describe hierarchy and structure. Internally, specifications are automatically translated to either temporal logic or LOTOS, depending on the application domain and the approach envisaged. The verification approach will use temporal logic as an intermediate language to capture, refine and process the specifications. VHDL descriptions will be internally translated into petri-net models from which transition systems will be generated, which will be checked against the specifications. Structural properties will be analysed directly in the PN model and interpreted in the VHDL description. The transformation approach will use LOTOS to refine the specification through the use of formal methodology. This approach will specifically target the synthesis of communication controllers. The tools developed will be integrated with the LAMBDA system, the most advanced general theorem-prover framework. Industrial demonstrators are planned in the fields of communications, advanced general-purpose processors and embedded control systems. Fields of science engineering and technologyelectrical engineering, electronic engineering, information engineeringelectronic engineeringcontrol systems Programme(s) FP3-ESPRIT 3 - Specific research and technological development programme (EEC) in the field of information technologies, 1990-1994 Topic(s) Data not available Call for proposal Data not available Funding Scheme Data not available Coordinator TECNOLOGIA GRUPO INI SA EU contribution No data Address PLAZA DEL MARQUES DE SALAMANCA, 3-4 28006 MADRID Spain See on map Total cost No data Participants (7) Sort alphabetically Sort by EU Contribution Expand all Collapse all Brunel University United Kingdom EU contribution No data Address Howell Building UB8 3PH Uxbridge See on map Total cost No data Italtel Società Italiana Telecomunicazioni SpA Italy EU contribution No data Address Castelletto di Settimo Milanese 20019 Milano See on map Total cost No data KURATORIUM OFFIS Germany EU contribution No data Address AMMERLANDER HEERSTRAßE 114-118 26129 OLDENBURG See on map Total cost No data Siemens AG Germany EU contribution No data Address Otto-Hahn-Ring 6 81739 München See on map Total cost No data TELEFONICA Spain EU contribution No data Address EMILIO VARGAS, 6 28043 MADRID See on map Total cost No data UNIVERSITAT POLITECNICA DE MADRID Spain EU contribution No data Address CAMPUS DE MONTEGANCEDO 28660 MADRID See on map Total cost No data UNIVERSITÄT PASSAU Germany EU contribution No data Address INNSTRAßE 33 94032 PASSAU See on map Total cost No data
