Cel
The objective of FORMAT is to reduce the design time for complex hardware modules by providing a set of system-level methods and design tools supporting an enhanced version of VHDL. Emphasis will be placed on formal verification and synthesis methods, whose introduction is expected to lead not only to designs of greater reliability but also to earlier recognition of errors in the design cycle. A transformation approach will also be explored.
FORMAT will specify and develop a graphical front-end and a specification language (VHDL-S) for use by designers. The graphical interface will use timing diagrams augmented to describe hierarchy and structure. Internally, specifications are automatically translated to either temporal logic or LOTOS, depending on the application domain and the approach envisaged.
The verification approach will use temporal logic as an intermediate language to capture, refine and process the specifications. VHDL descriptions will be internally translated into petri-net models from which transition systems will be generated, which will be checked against the specifications. Structural properties will be analysed directly in the PN model and interpreted in the VHDL description.
The transformation approach will use LOTOS to refine the specification through the use of formal methodology. This approach will specifically target the synthesis of communication controllers. The tools developed will be integrated with the LAMBDA system, the most advanced general theorem-prover framework.
Industrial demonstrators are planned in the fields of communications, advanced general-purpose processors and embedded control systems.
Dziedzina nauki
Temat(-y)
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28006 MADRID
Hiszpania