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Radiation Hard Resistive Random-Access Memory

Periodic Reporting for period 1 - R2RAM (Radiation Hard Resistive Random-Access Memory)

Reporting period: 2015-01-01 to 2016-12-31

The development of a radiation hard non‐volatile memory technology by using standard CMOS silicon processing was the main goal of this project. Since standard silicon memories, such as flash memories tend to fail under irradiation, a new approach is envisaged: the development of a specific memory technology, so called resistive random‐access memory (RRAM), which is able to sustain heavy ions and other charged particles. The radiation-induced leakage effects were minimized by using edge-less transistors (ELT). The non-volatile 1 Mbit memory chip was fabricated in IHP’s 250nm CMOS process line; the total area occupancy is 64 mm2. The 1T-1R memory cells are constituted by a select ELT transistor, which also sets the current compliance, whose drain is in series to a Metal-Insulator- Metal (MIM) stack. The MIM cell integrated on the metal line 2 of the CMOS process is a TiN/HfO2/Ti/TiN stack. The MIM cells area is 700 x 700 nm2. The relevant electrical parameters were defined for the RRAM memory and monitored during reliability characterization. The reliability assessment was carried out through a specific set of measurements performed either with a dedicated testing instrument called RIFLE (Research Instrument for FLash Evaluation) for the array testing. Array testing allows obtaining large statistical information about writing/reading behaviors of the memory.
The 1Mbit test vehicle was the result of the ensemble of eight 128kbit modules each having its own decoding scheme, ATD (Address Transition Detection) and sense amplifier. The test vehicle allowed a systematic characterization of the technology before, during and after the exposure to radiation. TID, proton and heavy ion characterization was performed by using a protected mother board and a daughter board hosting the 1Mbit test vehicle. The total ionizing dose (TID) can result in device failures. In TID irradiation campaign, the dose was ramped up until 500 krad, without any loss of data. Two additional types of radiation have been used to evaluate the radiation hardness: Xenon ions with 1200 MeV energy and protons with 52 MeV energy. Caused by the high fluence of 1011 cm-2 at 52 MeV (protons) and 106 cm-2 at 1200 MeV (Xenon) for 9 respectively 15 min, the LRS states of all cells were switched to HRS. After the readout procedure, the LRS states could be recovered completely by a standard set process. During the proton and heavy ion irradiation campaign, no ruptures have been observed in the memory circuitry.
Besides all possible architectural approaches and mitigation techniques of course the first issue to be considered in a rad-hard NVM (Non Volatile Memory) is the cell. A scenario of all possible FEOL and BEOL base NVM cells have been discussed under the point of view of a possible space application.
R2RAM target was to provide a rad-hard product able to be used in a standard package.
In order to evaluate the behavior of RRAM arrays under different temperature environment, electrical characterization on wafer level with thermo chuck (-40 °C to +150 °C) was required.
Finally, the 1 Mbit array test chip was successfully fabricated and assembled. IHP evaluated the standard CMOS process for integration of 1Mbit RRAM arrays to enable RRAM utilization in radiation hard applications. The 1T-1R memory cells are constituted by a select ELT transistor manufactured in IHP’ 250 nm CMOS technology.
Finally, the evaluation of the Design Rules for manufacturability from technology point of view and their implementation as DRC and LVS in Cadence Assura in order to assure manufacturability was evaluated
The memory test vehicle designed for the implementation of a non-volatile memory macro including the following features:
• 1Mbit logical array (2Mbit physical);
• 250nm CMOS IHP technology;
• Radiation-hardened by design architecture, circuits and pads;
• Die area of 61mm2 (X=6.036mm Y=10.102mm);
Irradiation tests were delivered in Jyvaskyla for SEE part where first of all resistance against hard errors (SEL, SEGR) were evaluated using Xe ions at the maximum energy available. In addition, equipment and instrumentation used in these tests were introduced. These are based on the practices obeyed at Radiation Effects Facility, RADEF, which is located at the accelerator laboratory of the department of physics of University of Jyväskylä, Finland.
R2RAM tried to extract all good features of RRAM technology and bring this technology to maturity. One of the most important tasks was to fully develop the control logic for RRAM array such that is supports the advance flexibility features and trade-off between the power/performance/reliability.
R2RAM consortium represented the combination between the research institutions at the source of the expertise in respect to memory device development and characterization. With R2RAM technical approach, including in parallel device, technology and circuit development in the area of Radiation hard memories, and carefully designed consortium we can achieve synergetic collaboration fully in line with the business strategy of European industry.
With the successful RRAM device of the R2RAM project, the new perspective for investing in more miniaturized devices and systems will be possible. Furthermore, the flexibility approach of R2RAM that is embedded in each level of our research approach will enable new functionalities and system reconfigurability according to application needs which was not possible before.
By designing a rad-hard complete memory with RRAM Technology, the industrial partner will strengthen its position inside the market of Radiation hard memories. In this scenario the already existing partnership with IHP will be reinforced to target ROTPs with the existing 250nm CMOS technology. The expected time frame for this approach is expected to be no more than two years where at the end at least a couple of products (e.g. 128kbit and 1Mbit ROTPs) are expected and one IOD (In Orbit Demonstration) to be completed. Currently the consortium is discussing the opportunity with ESA to be funded in the frame of the General Support Technology Programme (GSTP).
1 Mbit memory chip assembled into a DIL 48 package (without lid).