SPACE ETHERNET PHYSICAL LAYER TRANSCEIVER

Informations projet

SEPHY

N° de convention de subvention: 640243

DOI

10.3030/640243

Projet clôturé

Date de signature de la CE 17 Avril 2015

Date de début 1 Mai 2015

Date de fin 31 Decembre 2018

Financé au titre de

• INDUSTRIAL LEADERSHIP - Leadership in enabling and industrial technologies – Space

Coût total

€ 3 115 222,50

Contribution de l’UE

€ 3 115 222,50

Coordonné par

ARQUIMEA AEROSPACE DEFENCE AND SECURITY SL
Spain

CORDIS fournit des liens vers les livrables publics et les publications des projets HORIZON.

Les liens vers les livrables et les publications des projets du 7e PC, ainsi que les liens vers certains types de résultats spécifiques tels que les jeux de données et les logiciels, sont récupérés dynamiquement sur OpenAIRE .

Livrables

Documents, reports (10)

SEPHY Datasheet 2

This document will gather all technical data obtained from the architectural design until the final design validation and release.

Report on Surveillance Activities

Report including the most relevant items for the SEPHY project, as well as the analysis of the eventual required modifications of SEPHY accordingly to the external advances.

Report on Technical Feasibility of Space Grade 1 Gbps Ethernet Transceivers

This report will analyse the feasibility of implementing space grade transceivers for the two options considered for gigabit.

Report on Requirements for Space Grade 1Gbps Ethernet Transceivers

This report will provide the detailed specifications of the different analogue and digital blocks required to implement the two options considered for gigabit.

SEPHY Datasheet 1

This document will gather all technical data obtained from the architectural design until the final design validation and release.

SEPHY Datasheet 3

This document will gather all technical data obtained from the architectural design until the final design validation and release.

Post-Project Dissemination Plan

Report defining the dissemination strategy to be carried out once the project is finished.

Requirements Specification Document

This document will collect the requirements to be used for PHY design, verification and validation.

Report on Contributions to standards

This report will summarize the activities and contributions made to the ESA, NASA and JAXA standardization activities with regards to ECSS and CCSDS standardization of TTEthernet in order to push the use of Ethernet in space.

Report on Comparison and Selection of Space Grade 1Gbps Ethernet Transceivers

This deliverable will discuss which option is considered best for a 1 Gbps transceiver taking into account technical feasibility and application requirements.

Websites, patent fillings, videos etc. (2)

Website, Social Networks Profiles and AdWords Campaign

Brief document describing the website and social network profiles set up during the first three months of the project.

Project factsheet and logo

Brief description of SEPHY factsheet and logo generated at the beginning of the project.

Publications

Conference proceedings (6)

Eine Methode zur Verifikation von Mixed-Signal-ASIC

Auteurs: A. Breitenreiter, J. López, P. Reviriego, D. González and M. Krstic
Publié dans: Proceedings Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2017), 2017, Page(s) 73-76
Éditeur: VDE Verlag

SEPHY: An Ethernet Physical Layer Transceiver for Space

Auteurs: J. Lopez, P. Reviriego, M. Sanchez-Renedo, V. Petrovic, J.F. Dufour, J.S. Weil
Publié dans: Proc. 6th International Workshop on Analogue and Mixed-Signal Integrated Circuits for Space Applications (AMICSA 2016), 2016, Page(s) 126-127
Éditeur: none

An Automated Design and Verification Flow for Fault-Tolerant ASICs

Auteurs: A. Breitenreiter, M. Krstic
Publié dans: Proceedings Biannual European - Latin American Summer School on Design, Test and Reliability (BELAS 2017), 2017
Éditeur: none

A Methodology to Verify Digital IP's within Mixed-Signal Systems

Auteurs: Navaneetha Channiganathota Manjappa, Anselm Breitenreiter, Markus Ulbricht, Milos Krstic
Publié dans: 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2018, Page(s) 162-165, ISBN 978-1-5386-5754-6
Éditeur: IEEE
DOI: 10.1109/ddecs.2018.00036

Flip-Flop SEUs Mitigation through Partial Hardening of Internal Latch and Adjustment of Clock Duty Cycle

Auteurs: Yuanqing Li, Anselm Breitenreiter, Marko Andjelkovic, Oliver Schrape, Milos Krstic
Publié dans: 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2018, Page(s) 9-14, ISBN 978-1-5386-5754-6
Éditeur: IEEE
DOI: 10.1109/ddecs.2018.00009

A 10/100 Ethernet Transceiver for Space Applications

Auteurs: J. Lopez, J. Torreño, U. Gutierro, P. Reviriego, E. Pun, A. Breitenreiter, Y. Li, M. Krstic
Publié dans: 7th International Workshop on Analogue and Mixed-Signal Integrated Circuits for Space Applications (AMICSA 2018), 2018
Éditeur: none

Peer reviewed articles (1)

The space ethernet physical layer transceiver (sephy) project: a step towards reliable ethernet in space

Auteurs: Pedro Reviriego, Jesus Lopez, Manuel Sanchez-Renedo, Vladimir Petrovic, Jean-Francois Dufour, Jean-Sebastien Weil
Publié dans: IEEE Aerospace and Electronic Systems Magazine, Numéro 32/1, 2017, Page(s) 24-28, ISSN 0885-8985
Éditeur: Institute of Electrical and Electronics Engineers
DOI: 10.1109/maes.2017.160007