Periodic Reporting for period 1 - TCLS ARM FOR SPACE (Feasibility and Definition of a Triple Core Lockstep ARM System-on-Chip for Space Applications)
Reporting period: 2015-02-01 to 2017-02-28
Space domain, covering launchers and satellites, is a perfect target for embedded systems that require high performance control and data processing combined with safety features to ensure the execution of the mission. One of the main challenges of space integrated circuits is to resist to radiations. In addition to the use of rad-hardened technology, different mechanisms can improve the behavior of a function facing a radiation event.
The TCLS ARM FOR SPACE project aims at retargeting an ARM processor designed for terrestrial applications for space applications by incorporating an innovative mechanism named Triple Core Lockstep (TCLS) and demonstrating it in a laboratory environment.
So TCLS ARM FOR SPACE targets the following high level objectives:
- Bring one of the mainstream CPUs with the largest software eco-system into the space sector
- Establish a radiation hardened methodology for this CPU making it attractive to both space and terrestrial applications
- Evaluate both single processor core and TCLS triple core in terms of performance, power and radiation tolerance
- Study its portability to European STM65nm high performance hardened semiconductor technology
- Perform a breadboarding of System-on-Chip elements on a FPGA platform
In summary, this project has pioneered a fully European high-performance and low-power processor technology for space market, with implementation of an innovative protection mechanism and its evaluation and technical assessment before implementation in future space applications,.
In a first step, Airbus DS has collected the stakeholders’ needs to generate a consolidated requirement specifications for both a new ARM-based System on Chip and for the hardened by triplication mechanism called TCLS (Triple Core LockStep). Then an architectural concept of a TCLS System on Chip (SoC) with its interfaces has been defined before prototyping on an hardware board.
The TCLS voter logic block itself has been developed by ARM with three Cortex-R5 and validated by simulation with fault injections. Then the TCLS has been synthesized on the STM65nm Rad Hard technology to produce netlists before the physical implementation step. The objective was to compare different implementations in term of area and performances.
In parallel, an analysis of the chip sensitivity based on the sensitivity figures (error rates) of the targeted 65nm technology has been performed.
At hardware level, a FPGA-based demonstrator board around the Cortex-R5 has been created, with development of a test software allowing to demonstrate the basic features of the implemented architecture with focus on benchmark tests.
Different publications have been issued during the project development, for DASIA 2015 2016 & 2017, ADCSS 2016, IEEE DSN and DFT. So the TCLS ARM FOR SPACE results have been shared on different conferences which allowed to obtain feedback from all the major actors of the space industry, including ESA and potential users of this technology.
This mechanism allows to detect an error but does not allow to identify which one of the two cores is in error. So the output shall be discarded to avoid failure propagation. That’s why it has been proposed to extend the Dual Core LockStep (DCLS) concept to a triplication concept named Triple Core LockStep (TCLS). Thanks to majority voting on the three cores, it can detect error but can also continue to output a set of correct signals, leading to no interruption of service, contrary on what can be achieved with DCLS. In addition, a mechanism of reinsertion of the erroneous core has been implemented, in order to come back to a situation similar to the situation before the error occurrence, minimizing the reinsertion process duration.
The TCLS ARM FOR SPACE paves the way to the availability of a new high performance processing core for Space, without any compromission on safety aspects, perfectly in line with the European Space industry increased needs for payload and platform applications.
So as a summary, the TCLS ARM FOR SPACE study has allowed to:
- Provide an improved fail functional ARM solution compared to existing fail safe methods
- Consolidate the features, functions and interfaces needed for a future chip covering the needs for the next generation of platform computers and payload data processing units
- Evaluate and implment an ARM-based subsystem
- Work on the architecture and technology assessment of several ARM implementations (single core, dual or triple core lock-step)
- Develop the TCLS triplication mechanism with a particular care to make it applicable not only to the Cortex-R5 but also to any other ARM Cortex-R core
- Obtain results of implementation on a Deep Submicron technology
- Share the development and results with all the major actors of the space industry through different conferences presentations
- Extend the partners know-how on the STM 65nm space technology
- Develop a technology with potential interests for terrestrial applications
This will be directly exploited by Airbus DS for the definition of the future ARM-based SoC under development for the Space Community, called DAHLIA (Deep submicron microprocessor for spAce rad Hard appLIcation Asic).
This will be also exploited for the creation of a standard TCLS Cortex-R5 FPGA solution under the ARM University Program that will enable researchers and universities to build low-cost error-tolerant systems using TCLS Cortex-R5 in commercial FPGAs for utilisation in CubeSATs and drones.
Further, ARM will also engage with its ecosystem partners to explore the use of TCLS in autonomous driving that requires fail functionality in many critical components as TCLS Cortex-R5 fits into the profile of fail-functional CPU sub-systems.