As state of the art of safety mechanisms implemented in processing cores, in its “standard” version, the Cortex-R5 offers a Dual-Core Lock Step configuration. In that case, two cores execute the same code and their outputs are compared at every cycle to detect errors. This feature is used mainly in safety-critical automotive and industrial control systems.
This mechanism allows to detect an error but does not allow to identify which one of the two cores is in error. So the output shall be discarded to avoid failure propagation. That’s why it has been proposed to extend the Dual Core LockStep (DCLS) concept to a triplication concept named Triple Core LockStep (TCLS). Thanks to majority voting on the three cores, it can detect error but can also continue to output a set of correct signals, leading to no interruption of service, contrary on what can be achieved with DCLS. In addition, a mechanism of reinsertion of the erroneous core has been implemented, in order to come back to a situation similar to the situation before the error occurrence, minimizing the reinsertion process duration.
The TCLS ARM FOR SPACE paves the way to the availability of a new high performance processing core for Space, without any compromission on safety aspects, perfectly in line with the European Space industry increased needs for payload and platform applications.
So as a summary, the TCLS ARM FOR SPACE study has allowed to:
- Provide an improved fail functional ARM solution compared to existing fail safe methods
- Consolidate the features, functions and interfaces needed for a future chip covering the needs for the next generation of platform computers and payload data processing units
- Evaluate and implment an ARM-based subsystem
- Work on the architecture and technology assessment of several ARM implementations (single core, dual or triple core lock-step)
- Develop the TCLS triplication mechanism with a particular care to make it applicable not only to the Cortex-R5 but also to any other ARM Cortex-R core
- Obtain results of implementation on a Deep Submicron technology
- Share the development and results with all the major actors of the space industry through different conferences presentations
- Extend the partners know-how on the STM 65nm space technology
- Develop a technology with potential interests for terrestrial applications
This will be directly exploited by Airbus DS for the definition of the future ARM-based SoC under development for the Space Community, called DAHLIA (Deep submicron microprocessor for spAce rad Hard appLIcation Asic).
This will be also exploited for the creation of a standard TCLS Cortex-R5 FPGA solution under the ARM University Program that will enable researchers and universities to build low-cost error-tolerant systems using TCLS Cortex-R5 in commercial FPGAs for utilisation in CubeSATs and drones.
Further, ARM will also engage with its ecosystem partners to explore the use of TCLS in autonomous driving that requires fail functionality in many critical components as TCLS Cortex-R5 fits into the profile of fail-functional CPU sub-systems.
