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Feasibility and Definition of a Triple Core Lockstep ARM System-on-Chip for Space Applications

Deliverables

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Publications

TCLS ARM for space

Author(s): Jean-Luc Poupat; Benoit Leroy, Tim Helfers
Published in: EUROSPACE - DASIA 2016 - The International Space System Engineering Conference, 2016

TCLS arm for space

Author(s): Jean-Luc Poupat; Benoit Leroy, Tim Helfers
Published in: EUROSPACE - DASIA 2015 - The International Space System Engineering Conference, 2015

Triple Core Lock Step (TCLS) ARM FOR SPACE

Author(s): XabierIturbe, Balaji Venu, EmreOzer
Published in: ADCSS 2016 - European Space Research and Technology Centre (ESTEC), 2016

Soft error vulnerability assessment of the real-time safety-related ARM Cortex-R5 CPU

Author(s): Xabier Iturbe, Balaji Venu, Emre Ozer
Published in: 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2016, Page(s) 91-96
DOI: 10.1109/DFT.2016.7684076

A Triple Core Lock-Step (TCLS) ARM® Cortex®-R5 Processor for Safety-Critical and Ultra-Reliable Applications

Author(s): Xabier Iturbe, Balaji Venu, Emre Ozer, Shidhartha Das
Published in: 2016 46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshop (DSN-W), 2016, Page(s) 246-249
DOI: 10.1109/DSN-W.2016.57

A Fail-Functional Automotive CPU Subsystem Architecture for Mitigating Single Point of Failures