Periodic Reporting for period 2 - WAYTOGO FAST (Which Architecture Yields Two Other Generations Of Fully depleted Advanced Substrate and Technologies)
Période du rapport: 2016-08-01 au 2017-12-31
The overarching goal of WAYTOGOFAST was to provide, thanks to an industrial European consortium covering the full value chain, a sustainable route to FDSOI technology for future CMOS nodes and maintain the European industry leadership in equipment, metrology, materials and IP/Design on this alternative More Moore technology.
The targeted technology node was ST’s 14 FDSOI and its extension to 14+ FDSOI to prepare the future introduction of the next full node (10 FDSOI). Although the technical arguments initially presented in favour of the FDSOI remained valid during the entire project duration, the market context evolved compared to the situation when the project was built. Thus, end of 2015, ST had to reconsider the way to reach this goal, taking into account two main factors: i) the slower adoption by the planned markets of the 14 FDSOI that was delaying the need for ST of this node for its own product lines ; ii) the forecasted lifetime of the 28 FDSOI.
On this basis, ST concluded that the best way to ensure the sustainability of the FDSOI technology in Europe was to focus its efforts in preparing the 28 FDSOI to answer the future needs of the targeted markets and to postpone its development on the 14 FDSOI nodes.
Due to the forecasted long lifetime of the 28 FDSOI technology platforms, and in line with the digital strategy of ST, an important R&D work is required in the next years to improve and tune their performance and to propose new options in order to better address mass markets like IoT and Automotive and also smaller markets with high added value like Space.
Consequently, it was decided that WAYTOGOFAST targeted products still aimed to achieve the original strategic target but by extending the scope of the 28nm node and supporting the 22/22+ nm nodes rather than the 14 and 14+ FDSOI technologies originally envisaged.
For ST, starting January 1st 2016, the developments aimed at qualifying a pilot line for the extensions of the 28 FDSOI platforms: i) Improved low-power 28 FDSOI (Ultra Low Power / Ultra Low Voltage); ii) Compatibility to higher voltage interfaces, up to 5V, for direct connection with batteries for simpler/cheaper IoT systems; iii) Compatibility of the CMOS process with the eNVM cell and iv) RF 28 FDSOI & Hardened 28 FDSOI for automotive, and space respectively.
The figure 1 explains the links between the requirements of the different targeted markets and the 5 axes of development of the project.
Therefore, the project worked on the most suitable generations of FDSOI technologies to answer the market requirements in the next 4 years. At the end of the project, the pilot line is ready to ramp in production with a qualified technology having its reliability demonstrated. During the project timeframe the SOI substrate for this FDSOI technology passed industrial maturity readiness level (SOITEC PILOT LINE), and so is the FD CMOS technology platform built on it by STMicroelectronics and GlobalFoundries.
The targeted technology node was ST’s 14 FDSOI and its extension to 14+ FDSOI to prepare the future introduction of the next full node (10 FDSOI). Although the technical arguments initially presented in favour of the FDSOI remained valid during the entire project duration, the market context evolved compared to the situation when the project was built. Thus, end of 2015, ST had to reconsider the way to reach this goal, taking into account two main factors: i) the slower adoption by the planned markets of the 14 FDSOI that was delaying the need for ST of this node for its own product lines ; ii) the forecasted lifetime of the 28 FDSOI.
On this basis, ST concluded that the best way to ensure the sustainability of the FDSOI technology in Europe was to focus its efforts in preparing the 28 FDSOI to answer the future needs of the targeted markets and to postpone its development on the 14 FDSOI nodes.
Due to the forecasted long lifetime of the 28 FDSOI technology platforms, and in line with the digital strategy of ST, an important R&D work is required in the next years to improve and tune their performance and to propose new options in order to better address mass markets like IoT and Automotive and also smaller markets with high added value like Space.
Consequently, it was decided that WAYTOGOFAST targeted products still aimed to achieve the original strategic target but by extending the scope of the 28nm node and supporting the 22/22+ nm nodes rather than the 14 and 14+ FDSOI technologies originally envisaged.
For ST, starting January 1st 2016, the developments aimed at qualifying a pilot line for the extensions of the 28 FDSOI platforms: i) Improved low-power 28 FDSOI (Ultra Low Power / Ultra Low Voltage); ii) Compatibility to higher voltage interfaces, up to 5V, for direct connection with batteries for simpler/cheaper IoT systems; iii) Compatibility of the CMOS process with the eNVM cell and iv) RF 28 FDSOI & Hardened 28 FDSOI for automotive, and space respectively.
The figure 1 explains the links between the requirements of the different targeted markets and the 5 axes of development of the project.
Therefore, the project worked on the most suitable generations of FDSOI technologies to answer the market requirements in the next 4 years. At the end of the project, the pilot line is ready to ramp in production with a qualified technology having its reliability demonstrated. During the project timeframe the SOI substrate for this FDSOI technology passed industrial maturity readiness level (SOITEC PILOT LINE), and so is the FD CMOS technology platform built on it by STMicroelectronics and GlobalFoundries.
The technical achievements of the project are described in the Final report annexed to the 2nd periodic report and are related to:
Process Modules for 14nm and beyond and M3DI:
- 2XFD-SOI topics for ULP applications
- Lithography and specific Metrology
- Physical Characterization (MEIS, HR-XRD, CD-SAXS)
Pathfinding integration for M3DI:
- Siltronic achieved world record of low threading dislocation density for graded buffers of 50% and 70% germanium content.
- Soitec and CEA-Leti developed a new process to achieve good quality, cost effective and very low surface roughness SOI product with no thermal treatment and with very good thickness uniformity control.
- DSD demonstrated a huge improvement in the surface defectivity of their process in single wafer cleaning tool thanks to a deep understanding of physical and chemical mechanism
- EVG new bonding platform to the required level of specification in terms of defectivity.
- INPG new method for the metrology of Deep Interface Traps (Dit)
Devices:
- SiGe channel for PMOS transistor combined with HfO2 dielectric integration allowing a significant performance enhancement versus reference technology 28FDSOI.
- FDSOI Substrate pilot line: appropriate metrology tools (HSEB), the monitoring of wafer quality compliance with respect to device requirements (ST and GF) More than 35000 substrates manufactured + more than 1000 wafers with a 15nm thick Buried Oxide wafers for next generation
collaboration allowed the development and implementation
mm-wave passives, oscillator IP and System-in-Package technology:
- Novel mm-wave interconnect technologies for polymer based redistribution layers (2 layers) in silicon based packages are designed and realized.
- Several resonant patch antennas for the new technology in the range of up to
- Numerous test structures and technology samples for the chosen eWLB technology and the novel Si-based packaging technology.
- 70 GHz mm-wave VCO with 22FDX with lower power consumption vs state of the art
IP design:
- New methods for hierarchical failure rate analysis in memories (approx. x200 times faster compared to the traditional Monte Carlo analysis methods)
- low power (<0.5W) wide range (25MHz to 300MHz) PLL generator-synchronization circuit at the 28nm cutting edge FD-SOI technology featuring 24 outputs with a low supply voltage (1.8V) and exceptionally low jitter values (<40ps at 125MHz output frequency)
- For the first time an industrial body bias compensation solution for FDSOI ULV/ULP and automotive products
- VCO with a novel architecture, demonstrating the highest frequency ever measured in 28nm. VCO exhibits an excellent DC to RF conversion efficiency and phase noise.
- a novel architecture enabling broadband operation while being compliant with 5G demands
- A high level of robustness of FDSOI28 process technology on a complex non-hardened and hardened instance, such as 32 bits ARM Cortex-M4 processors was proven.
- Co-integration between 28FDSOI CMOS architecture and PCM inserted right after contact ready for prototyping phase
Process Modules for 14nm and beyond and M3DI:
- 2XFD-SOI topics for ULP applications
- Lithography and specific Metrology
- Physical Characterization (MEIS, HR-XRD, CD-SAXS)
Pathfinding integration for M3DI:
- Siltronic achieved world record of low threading dislocation density for graded buffers of 50% and 70% germanium content.
- Soitec and CEA-Leti developed a new process to achieve good quality, cost effective and very low surface roughness SOI product with no thermal treatment and with very good thickness uniformity control.
- DSD demonstrated a huge improvement in the surface defectivity of their process in single wafer cleaning tool thanks to a deep understanding of physical and chemical mechanism
- EVG new bonding platform to the required level of specification in terms of defectivity.
- INPG new method for the metrology of Deep Interface Traps (Dit)
Devices:
- SiGe channel for PMOS transistor combined with HfO2 dielectric integration allowing a significant performance enhancement versus reference technology 28FDSOI.
- FDSOI Substrate pilot line: appropriate metrology tools (HSEB), the monitoring of wafer quality compliance with respect to device requirements (ST and GF) More than 35000 substrates manufactured + more than 1000 wafers with a 15nm thick Buried Oxide wafers for next generation
collaboration allowed the development and implementation
mm-wave passives, oscillator IP and System-in-Package technology:
- Novel mm-wave interconnect technologies for polymer based redistribution layers (2 layers) in silicon based packages are designed and realized.
- Several resonant patch antennas for the new technology in the range of up to
- Numerous test structures and technology samples for the chosen eWLB technology and the novel Si-based packaging technology.
- 70 GHz mm-wave VCO with 22FDX with lower power consumption vs state of the art
IP design:
- New methods for hierarchical failure rate analysis in memories (approx. x200 times faster compared to the traditional Monte Carlo analysis methods)
- low power (<0.5W) wide range (25MHz to 300MHz) PLL generator-synchronization circuit at the 28nm cutting edge FD-SOI technology featuring 24 outputs with a low supply voltage (1.8V) and exceptionally low jitter values (<40ps at 125MHz output frequency)
- For the first time an industrial body bias compensation solution for FDSOI ULV/ULP and automotive products
- VCO with a novel architecture, demonstrating the highest frequency ever measured in 28nm. VCO exhibits an excellent DC to RF conversion efficiency and phase noise.
- a novel architecture enabling broadband operation while being compliant with 5G demands
- A high level of robustness of FDSOI28 process technology on a complex non-hardened and hardened instance, such as 32 bits ARM Cortex-M4 processors was proven.
- Co-integration between 28FDSOI CMOS architecture and PCM inserted right after contact ready for prototyping phase
The overall impact is to strengthen the European supply side of ECS with an original and complementary More Moore technology. Alongside the mainstream CMOS, the project speeded up the competitiveness of the FDSOI with a higher performance architecture node and substrate, pushing its manufacturing update within a short-time to market, demonstrating its superiority on low power applications (mobile convergence, smart connected objects and Internet of Things).
WAYTOGOFAST Pilot line is thus fully in line with the ECSEL Vision and Mission statements and with the associated SRA.
WAYTOGOFAST Pilot line is thus fully in line with the ECSEL Vision and Mission statements and with the associated SRA.