Which Architecture Yields Two Other Generations Of Fully depleted Advanced Substrate and Technologies

CORDIS fournit des liens vers les livrables publics et les publications des projets HORIZON.

Les liens vers les livrables et les publications des projets du 7e PC, ainsi que les liens vers certains types de résultats spécifiques tels que les jeux de données et les logiciels, sont récupérés dynamiquement sur OpenAIRE .

Publications

Back-gate bias effect on UTBB-FDSOI non-linearity performance

Auteurs: B. Kazemi Esfeh, V. Kilchytska, B. Parvais, N. Planes, M. Haond, D. Flandre, J.-P. Raskin
Publié dans: 2017 47th European Solid-State Device Research Conference (ESSDERC), 2017, Page(s) 148-151, ISBN 978-1-5090-5978-2
Éditeur: IEEE
DOI: 10.1109/ESSDERC.2017.8066613

Comparative study of non-linearities in 28 nm node FDSOI and Bulk MOSFETs

Auteurs: V. Kilchytska, B. Kazemi Esfeh, C. Gimeno, B. Parvais, N. Planes, M. Haond, J.-P. Raskin, D. Flandre
Publié dans: 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2017, Page(s) 128-131, ISBN 978-1-5090-5313-1
Éditeur: IEEE
DOI: 10.1109/ULIS.2017.7962581

Back-gate bias effect on FDSOI MOSFET RF Figures of Merits and parasitic elements

Auteurs: B. Kazemi Esfeh, V. Kilchytska, B. Parvais, N. Planes, M. Haond, D. Flandre, J.-P. Raskin
Publié dans: 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2017, Page(s) 228-230, ISBN 978-1-5090-5313-1
Éditeur: IEEE
DOI: 10.1109/ULIS.2017.7962569

Mechanical simulation of stress engineering solutions in highly strained p-type FDSOI MOSFETs for 14-nm node and beyond

Auteurs: A. Idrissi-El Oudrhiri, S. Martinie, J-C. Barbe, O. Rozeau, C. Le Royer, M-A. Jaud, J. Lacord, N. Bernier, L. Grenouillet, P. Rivallin, J. Pelloux-Prayer, M. Casse, M. Mouis
Publié dans: 2015 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2015, Page(s) 206-209, ISBN 978-1-4673-7860-4
Éditeur: IEEE
DOI: 10.1109/SISPAD.2015.7292295

Scatterometry control for multiple electron beam lithography

Auteurs: Yoann Blancquaert, Nivea Figueiro, Thibault Labbaye, Francisco Sanchez, Stephane Heraud, Roy Koret, Matthew Sendelbach, Ralf Michel, Shay Wolfling, Stephane Rey, Laurent Pain
Publié dans: Metrology, Inspection, and Process Control for Microlithography XXXI, 2017, Page(s) 101451F
Éditeur: SPIE
DOI: 10.1117/12.2261389

Smart solutions for efficient dual strain integration for future FDSOI generations

Auteurs: A. Bonnevialle, C. Le Royer, Y. Morand, S. Reboh, C. Plantier, N. Rambal, J.-P. Pedini, S. Kerdiles, P. Besson, J.-M. Hartmann, D. Marseilhan, B. Mathieu, R. Berthelon, M. Casse, F. Andrieu, D. Rouchon, O. Weber, F. Boeuf, M. Haond, A. Claverie, M. Vinet
Publié dans: 2016 IEEE Symposium on VLSI Technology, 2016, Page(s) 1-2, ISBN 978-1-5090-0638-0
Éditeur: IEEE
DOI: 10.1109/VLSIT.2016.7573406

Field mapping of semiconductor devices in a transmission electron microscope with nanometre scale resolution by off-axis electron holography and precession electron diffraction

Auteurs: David Cooper, Nicolas Bernier, Jean-Luc Rouviere
Publié dans: 2015 IEEE 15th International Conference on Nanotechnology (IEEE-NANO), 2015, Page(s) 777-780, ISBN 978-1-4673-8156-7
Éditeur: IEEE
DOI: 10.1109/NANO.2015.7388725

Vertically stacked-NanoWires MOSFETs in a replacement metal gate process with inner spacer and SiGe source/drain

Auteurs: S. Barraud, V. Lapras, M.P. Samson, L. Gaben, L. Grenouillet, V. Maffini-Alvaro, Y. Morand, J. Daranlot, N. Rambal, B. Previtalli, S. Reboh, C. Tabone, R. Coquand, E. Augendre, O. Rozeau, J. M. Hartmann, C. Vizioz, C. Arvet, P. Pimenta-Barros, N. Posseme, V. Loup, C. Comboroure, C. Euvrard, V. Balan, I. Tinti, G. Audoit, N. Bernier, D. Cooper, Z. Saghi, F. Allain, A. Toffoli, O. Faynot, M. Vinet
Publié dans: 2016 IEEE International Electron Devices Meeting (IEDM), 2016, Page(s) 17.6.1-17.6.4, ISBN 978-1-5090-3902-9
Éditeur: IEEE
DOI: 10.1109/IEDM.2016.7838441

Performance and layout effects of SiGe channel in 14nm UTBB FDSOI: SiGe-first vs. SiGe-last integration

Auteurs: R. Berthelon, F. Andrieu, P. Perreau, E. Baylac, A. Pofelski, E. Josse, D. Dutartre, A. Claverie, M. Haond
Publié dans: 2016 46th European Solid-State Device Research Conference (ESSDERC), 2016, Page(s) 127-130, ISBN 978-1-5090-2969-3
Éditeur: IEEE
DOI: 10.1109/ESSDERC.2016.7599604

Design / technology co-optimization of strain-induced layout effects in 14nm UTBB-FDSOI CMOS: Enablement and assessment of continuous-RX designs

Auteurs: R. Berthelon, F. Andrieu, E. Josse, R. Bingert, O. Weber, E. Serret, A. Aurand, S. Delmedico, V. Farys, C. Bernicot, E. Bechet, E. Bernard, T. Poiroux, D. Rideau, P. Scheer, E. Baylac, P. Perreau, M.A. Jaud, J. Lacord, E. Petitprez, A. Pofelski, S. Ortolland, P. Sardin, D. Dutartre, A. Claverie, M. Vinet, J.C. Marin, M. Haond
Publié dans: 2016 IEEE Symposium on VLSI Technology, 2016, Page(s) 1-2, ISBN 978-1-5090-0638-0
Éditeur: IEEE
DOI: 10.1109/VLSIT.2016.7573425

A novel dual isolation scheme for stress and back-bias maximum efficiency in FDSOI Technology

Auteurs: R. Berthelon, F. Andrieu, P. Perreau, D. Cooper, F. Roze, O. Gourhant, P. Rivallin, N. Bernier, A. Cros, C. Ndiaye, E. Baylac, E. Souchier, D. Dutartre, A. Claverie, O. Weber, E. Josse, M. Vinet, M. Haond
Publié dans: 2016 IEEE International Electron Devices Meeting (IEDM), 2016, Page(s) 17.7.1-17.7.4, ISBN 978-1-5090-3902-9
Éditeur: IEEE
DOI: 10.1109/IEDM.2016.7838442

Impact of the design layout on threshold voltage in SiGe channel UTBB-FDSOI pMOSFET

Auteurs: R. Berthelon, F. Andrieu, S. Ortolland, R. Nicolas, T. Poiroux, E. Baylac, D. Dutartre, E. Josse, A. Claverie, M. Haond
Publié dans: 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2016, Page(s) 88-91, ISBN 978-1-4673-8609-8
Éditeur: IEEE
DOI: 10.1109/ULIS.2016.7440059

Mechanical simulations of BOX creep for strained FDSOI

Auteurs: R. Berthelon, F. Andrieu, B. Mathieu, D. Dutartre, C. Le Royer, M. Vinet, A. Claverie
Publié dans: 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2017, Page(s) 91-94, ISBN 978-1-5090-5313-1
Éditeur: IEEE
DOI: 10.1109/ULIS.2017.7962609

Impact of strain on access resistance in planar and nanowire CMOS devices

Auteurs: R. Berthelon, F. Andneu, F. Triozon, M. Casse, L. Bourdet, G. Ghibaudo, D. Rideau, Y. M. Niquet, S. Barraud, P. Nguyen, C. Le Royer, J. Lacord, C. Tabone, O. Rozeau, D. Dutartre, A. Claverie, E. Josse, F. Arnaud, M. Vinet
Publié dans: 2017 Symposium on VLSI Technology, 2017, Page(s) T224-T225, ISBN 978-4-86348-605-8
Éditeur: IEEE
DOI: 10.23919/VLSIT.2017.7998180

Physical transport simulation for path-finding and device optimization

Auteurs: M. Karner, Z. Stanojevic, O. Baumgartner, HW. Karner, C. Kernstock, H. Demel, F. Mitterbauer
Publié dans: 2016 IEEE Silicon Nanoelectronics Workshop (SNW), 2016, Page(s) 208-209, ISBN 978-1-5090-0726-4
Éditeur: IEEE
DOI: 10.1109/SNW.2016.7578054

Phase-space solution of the subband Boltzmann transport equation for nano-scale TCAD

Auteurs: Z. Stanojevic, M. Karner, O. Baumgartner, H. W. Karner, C. Kernstock, H. Demel, F. Mitterbauer
Publié dans: 2016 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2016, Page(s) 65-67, ISBN 978-1-5090-0818-6
Éditeur: IEEE
DOI: 10.1109/SISPAD.2016.7605149

Vertically stacked nanowire MOSFETs for sub-10nm nodes: Advanced topography, device, variability, and reliability simulations

Auteurs: M. Karner, O. Baumgartner, Z. Stanojevic, F. Schanovsky, G. Strof, C. Kernstock, H. W. Karner, G. Rzepa, T. Grasset
Publié dans: 2016 IEEE International Electron Devices Meeting (IEDM), 2016, Page(s) 30.7.1-30.7.4, ISBN 978-1-5090-3902-9
Éditeur: IEEE
DOI: 10.1109/IEDM.2016.7838516

Towards physics-based DTCO for performance of advanced technology nodes

Auteurs: Z. Stanojevic, O. Baumgartner, M. Karner, C. Kernstock, H. W. Karner, H. Demel, G. Strof, F. Mitterbauer
Publié dans: 2017 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2017, Page(s) 245-248, ISBN 978-4-86348-610-2
Éditeur: IEEE
DOI: 10.23919/SISPAD.2017.8085310

TCAD-based characterization of logic cells: Power, performance, area, and variability

Auteurs: HW. Karner, C. Kernstock, Z. Stanojevic, O. Baumgartner, F. Schanovsky, M. Karner, D. Helms, R. Eilers, M. Metzdorf
Publié dans: 2017 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 2017, Page(s) 1-2, ISBN 978-1-5090-5805-1
Éditeur: IEEE
DOI: 10.1109/VLSI-TSA.2017.7942453

22nm FDSOI technology for emerging mobile, Internet-of-Things, and RF applications

Auteurs: R. Carter, J. Mazurier, L. Pirro, J-U. Sachse, P. Baars, J. Faul, C. Grass, G. Grasshoff, P. Javorka, T. Kammler, A. Preusse, S. Nielsen, T. Heller, J. Schmidt, H. Niebojewski, P-Y. Chou, E. Smith, E. Erben, C. Metze, C. Bao, Y. Andee, I. Aydin, S. Morvan, J. Bernard, E. Bourjot, T. Feudel, D. Harame, R. Nelluri, H.-J. Thees, L. M-Meskamp, J. Kluth, R. Mulfinger, M. Rashed, R. Taylor, C. Weintraub
Publié dans: 2016 IEEE International Electron Devices Meeting (IEDM), 2016, Page(s) 2.2.1-2.2.4, ISBN 978-1-5090-3902-9
Éditeur: IEEE
DOI: 10.1109/IEDM.2016.7838029

Out-of-equilibrium body potential measurements in pseudo-MOSFET for biosensing

Auteurs: Licinius Benea, Maryline Bawedin, Cecile Delacour, Sorin Cristoloveanu, Irina Ionica
Publié dans: 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2017, Page(s) 19-22, ISBN 978-1-5090-5313-1
Éditeur: IEEE
DOI: 10.1109/ULIS.2017.7962590

BTI induced dispersion: Challenges and opportunities for SRAM bit cell optimization

Auteurs: F. Cacho, A. Cros, X. Federspiel, V. Huard, C. Roma
Publié dans: 2016 IEEE International Reliability Physics Symposium (IRPS), 2016, Page(s) 7C-1-1-7C-1-6, ISBN 978-1-4673-9137-5
Éditeur: IEEE
DOI: 10.1109/IRPS.2016.7574581

Localized STRASS Technique on Advanced FDSOI Platform: Highly Tensile Si Demonstration for Dual Strain CMOS Integration

Auteurs: A. Bonnevialle, S. Reboh, C. Le Royer, Y. Morand, J.-M. Hartmann, D. Rouchon, J.-M. Pedini, C. Tabone, N. Rambal, A. Payet, C. Plantier, F. Boeuf, M. Haond, A. Claverie, M. Vinet
Publié dans: 2016
Éditeur: E-MRS 2016 (European Material Research Society)

A New Method to Induce Local Tensile Strain in SOI Wafers: First Strain Results of the “BOX Creep” Technique”

Auteurs: A. Bonnevialle, C. Le Royer, Y. Morand, S. Reboh, J.-M. Pédini, A. Roule, D. Marseilhan, P. Besson, D. Rouchon, N. Bernier, C. Tabone, C. Plantier, M. Vinet,
Publié dans: 2015
Éditeur: 2015 International Conference on Solid State Devices and Materials (SSDM)

Ω-Gate Nanowire Transistors Realized by Sidewall Image Transfer Patterning: 35nm channel pitch and opportunities for stacked-Nanowires architectures

Auteurs: L. Gaben, S. Barraud, P. Pimenta-Barros, Y. Morand, J. Pradelles, M.-P. Samson, B. Previtali, P. Besson, F. Allain, S. Monfray, F. Boeuf, T. Skotnicki, F. Balestra3 and M. Vine
Publié dans: 2015
Éditeur: 2015 International Conference on Solid State Devices and Materials (SSDM)

Fast and Accurate solution of inverse problem for in-line monitoring of strain field determined by High Resolution X-Ray Diffraction Reciprocal Space Mapping

Auteurs: A DURAND, M KAUFLING, D LE-CUNFF, D ROUCHON, P GERGAUD
Publié dans: 2016
Éditeur: XTOP 2016 - 13th Biennial Conference on High-Resolution X-Ray Diffraction and Imaging

Design Technology Co-Optimization of 3D-monolithic standard cells and SRAM exploiting dynamic back-bias for ultra-low-voltage operation

Auteurs: F. Andrieu, R. Berthelon, R. Boumchedda, G. Tricaud, L. Brunet, P. Batude, B. Mathieu, E. Avelar, A. Ayres de Sousa, G. Cibrario, O. Rozeau, J. Lacord, O. Billoint, C. Fenouillet-Béranger, S. Guissi, D. Fried, P. Morin, J.P. Noel, B. Giraud, S. Thuries, F. Arnaud, M. Vinet
Publié dans: 2017
Éditeur: Electron Devices Meeting (IEDM), 2017 IEEE International

“Material and Device Innovation for Cost Effective CMOS Scaling Beyond 28nm”

Auteurs: W. Schwarzenbach, F. Allibert, C. Figuet, C. Girard and C. Maleville
Publié dans: 2016
Éditeur: ETCMOS Conference, 2016 (Emerging Technologies Communications Microsystems Optoelectronics)

“Beyond Silicon CMOS: Progress and challenges”

Auteurs: B.-Y. Nguyen, M.Sadaka, G.Gaudin, W. Schwarzenbach, K.Boudelle,C.Figuet and C.Maleville
Publié dans: 2016
Éditeur: CS ManTech Conference, 2016 (Compound Semiconductor Manufacturing Technology)

“Investigation of Hot Carrier reliability of SOI and sSOI transistors using Back Bias”

Auteurs: G. Besnard, X. Garros, A. Subirats, F. Andrieu, X. Federspiel, M. Rafik, W. Schwarzenbach, G. Reimbold, O. Faynot, S. Cristoloveanu and C. Mazure
Publié dans: 2015
Éditeur: VLSI-TSA Conference 2015 - International Symposium on VL Technology, Systems and Applications

“P-FET Co-Integration on Si and Strained SiGe Dual Channel Substrates Obtained by Ge Local Enrichment Technique”

Auteurs: Nguyen, S. Barraud, L. Hutin, C. Tabone, F. Glowacki, J.-M. Hartmann, M.-P. Samson†, L. Ecarnot, B.-Y. Nguyen¤, C. Maleville, C. Mazuré, O. Faynot, M. Vinet
Publié dans: 2015
Éditeur: IWNA Conference 2015

“High Mobility Materials on Insulator for Advanced Technology Nodes”

Auteurs: J. Widieza, F. Mazena, J-M. Hartmanna, Y. Bogumilowicza, E. Augendrea, C. Veytizoub, S. Solliera, M. Martinc, M-C. Rourea, V. Loupa, C. Euvrada, A. Seignarda, T. Baronc, R. Ciproc, F. Bassanic, A-M. Papona, C. Guedja, I. Huyetb, M. Rivoirea, P. Bessona, C. Figuetb, W. Schwarzenbachb, D. Delpratb and T. Signamarcheixa
Publié dans: 2015
Éditeur: ECS Chicago 2015 (Electrochemical Society Chicago Meeting)

“Designing with FD-SOI“ & “Interconnected World”.

Auteurs: J. Kunkel
Publié dans: 2015
Éditeur: SOITEC

“Substrate maturity+D61:M61+D61:M61 and readiness in large volume to support mass adoption of ULP FDSOI platforms”

Auteurs: C.Maleville
Publié dans: 2016
Éditeur: The annual SOI Silicon Valle

“Designing with FD-SOI Technologies”

Auteurs: C.Maleville
Publié dans: 2017
Éditeur: FD-SOI ForumShanghai 2017, FD-SOI Design Tutorial, SOI Workshop & Tutorial

“How innovation and eco-system in Europe can enable future requirements in automotive electronics”

Auteurs: N. Kernevez
Publié dans: 2015
Éditeur: Semicon Europa

“Engineered substrates for low-power devices”

Auteurs: T. Piliszczuk
Publié dans: 2015
Éditeur: Semicon Europa

“Novel chip embedding and interconnection technology for mm-wave System-in-Package (SiP) applications,”

Auteurs: C. Landesberger et al.
Publié dans: 2018
Éditeur: 12th Smart Systems Integration Conference, 2018

“Slow-wave coplanar strip line based Low-power 80-GHz Voltage Control Oscillator on 22-nm FDSOI technology,”

Auteurs: T. Lim et al.
Publié dans: 2017
Éditeur: Proc. of 2017 Asia Pacific Microwave Conference (APMC)

Investigation of hot carrier reliability of SOI and strained SOI transistors using back bias

Auteurs: G. Besnard, X. Garros, A. Subirats, F. Andrieu, X. Federspiel, M. Rafik, W. Schwarzenbach, G. Reimbold, O. Faynot, S. Cristoloveanu, C. Mazure
Publié dans: 2015 International Symposium on VLSI Technology, Systems and Applications, 2015, Page(s) 1-2, ISBN 978-1-4799-7375-0
Éditeur: IEEE
DOI: 10.1109/VLSI-TSA.2015.7117577

Performance and reliability of strained SOI transistors for advanced planar FDSOI technology

Auteurs: G. Besnard, X. Garros, A. Subirats, F. Andrieu, X. Federspiel, M. Rafik, W. Schwarzenbach, G. Reimbold, O. Faynot, S. Cristoloveanu
Publié dans: 2015 IEEE International Reliability Physics Symposium, 2015, Page(s) 2F.1.1-2F.1.5, ISBN 978-1-4673-7362-3
Éditeur: IEEE
DOI: 10.1109/IRPS.2015.7112691

Systematic evaluation of SOI Buried Oxide reliability for partially depleted and fully depleted applications

Auteurs: W. Schwarzenbach, C. Malaquin, F. Allibert, G. Besnard, B.-Y. Nguyen
Publié dans: 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2015, Page(s) 1-3, ISBN 978-1-5090-0259-7
Éditeur: IEEE
DOI: 10.1109/S3S.2015.7333496

Analysis and modelling of temperature effect on DIBL in UTBB FD SOI MOSFETs

Auteurs: A. S. N. Pereira, G. de Streel, N. Planes, M. Haond, R. Giacomini, D. Flandre, V. Kilchytska
Publié dans: 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2016, Page(s) 116-119, ISBN 978-1-4673-8609-8
Éditeur: IEEE
DOI: 10.1109/ULIS.2016.7440066

Threshold voltage and on-current Variability related to interface traps spatial distribution

Auteurs: V. Velayudhan, J. Martin-Martinez, M. Porti, C. Couso, R. Rodriguez, M. Nafria, X. Aymerich, C. Marquez, F. Gamiz
Publié dans: 2015 45th European Solid State Device Research Conference (ESSDERC), 2015, Page(s) 230-233, ISBN 978-1-4673-7135-3
Éditeur: IEEE
DOI: 10.1109/ESSDERC.2015.7324756

Electrical characterization of Random Telegraph Noise in back-biased Ultrathin Silicon-On-Insulator MOSFETs

Auteurs: Carlos Marquez, Noel Rodriguez, Francisco Gamiz, Akiko Ohata
Publié dans: 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2016, Page(s) 40-43, ISBN 978-1-4673-8609-8
Éditeur: IEEE
DOI: 10.1109/ULIS.2016.7440047

Impact of S/D tunneling in ultrascaled devices, a Multi-Subband Ensemble Monte Carlo study

Auteurs: C. Medina-Bailon, C. Sampedro, F. Gamiz, A. Godoy, L. Donetti
Publié dans: 2015 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2015, Page(s) 214-217, ISBN 978-1-4673-7860-4
Éditeur: IEEE
DOI: 10.1109/SISPAD.2015.7292297

Multi-Subband Ensemble Monte Carlo simulation of Si nanowire MOSFETs

Auteurs: Luca Donetti, Carlos Sampedro, Francisco Gamiz, Andres Godoy, Francisco J. Garcia-Ruiz, Ewan Towiez, Vihar P. Georgiev, Salvatore Maria Amoroso, Craig Riddet, Asen Asenov
Publié dans: 2015 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2015, Page(s) 353-356, ISBN 978-1-4673-7860-4
Éditeur: IEEE
DOI: 10.1109/SISPAD.2015.7292332

Confinement orientation effects in S/D tunneling

Auteurs: C. Medina-Bailon, C. Sampedro, F. Gamiz, A. Godoy, L. Donetti
Publié dans: 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2016, Page(s) 100-103, ISBN 978-1-4673-8609-8
Éditeur: IEEE
DOI: 10.1109/ULIS.2016.7440062

Physical modeling - A new paradigm in device simulation

Auteurs: Z. Stanojevic, O. Baumgartner, F. Mitterbauer, H. Demel, C. Kernstock, M. Karner, V. Eyert, A. France-Lanord, P. Saxe, C. Freeman, E. Wimmer
Publié dans: 2015 IEEE International Electron Devices Meeting (IEDM), 2015, Page(s) 5.1.1-5.1.4, ISBN 978-1-4673-9894-7
Éditeur: IEEE
DOI: 10.1109/IEDM.2015.7409631

Interest of SiCO low k=4.5 spacer deposited at low temperature (400°C) in the perspective of 3D VLSI integration

Auteurs: D. Benoit, J. Mazurier, B. Varadarajan, S. Chhun, S. Lagrasta, C. Gaumer, D. Galpin, C. Fenouillet-Beranger, D. Vo-Thanh, D. Barge, R. Duru, R. Beneyton, B. Gong, N. Sun, N. Chauvet, P. Ruault, D. Winandy, B. van Schravendijk, P. Meijer, O. Hinsinger
Publié dans: 2015 IEEE International Electron Devices Meeting (IEDM), 2015, Page(s) 8.6.1-8.6.4, ISBN 978-1-4673-9894-7
Éditeur: IEEE
DOI: 10.1109/IEDM.2015.7409656

Designing wit FD-SOI technologies

Auteurs: C.Maleville
Publié dans: 2017
Éditeur: Annual SOI Silicon Valley Symposium

Advanced CMOS Nodes (FDSOI, FinFET) usage for High Reliability Markets from Device and Design

Auteurs: P.Gupta
Publié dans: 2016
Éditeur: IRPS Conference

Engineered substrates for Moore and more than Moore's law: Device scaling: Entering the substrate era

Auteurs: Christophe Maleville
Publié dans: 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2015, Page(s) 1-5, ISBN 978-1-5090-0259-7
Éditeur: IEEE
DOI: 10.1109/S3S.2015.7333494

Low-variation SRAM bitcells in 22nm FDSOI technology

Auteurs: V. Joshi, H. Ramamurthy, S. Balasubramanian, S. Seo, H. Yoon, X. Zou, N. Chan, J. Yun, T. Klick, E. Smith, J. Schmid, R. vanBentum, J. Faul, C. Weintraub
Publié dans: 2017 Symposium on VLSI Technology, 2017, Page(s) T222-T223, ISBN 978-4-86348-605-8
Éditeur: IEEE
DOI: 10.23919/VLSIT.2017.7998179

The FDSOI history and its future

Auteurs: P.Flatresse
Publié dans: 2017
Éditeur: IPSOC

Keynote - The FDSOI saga

Auteurs: C.Mazure
Publié dans: 2017
Éditeur: Minalogic

SU3200 use case to enable Angström level FDSOI uniformity all wafers all points

Auteurs: N.Daval
Publié dans: 2017
Éditeur: Semicon Europea

Low latency digital regenerator for dual polarization QAM signals

Auteurs: Fred Buchali, Laurent Schmalen, Qian Hu, Di Che
Publié dans: 2015 European Conference on Optical Communication (ECOC), 2015, Page(s) 1-3, ISBN 978-8-4608-1741-3
Éditeur: IEEE
DOI: 10.1109/ECOC.2015.7341622

Preemphased Prime Frequency Multicarrier Bases ENOB Assessment and its Application for Optimizing a Dual-Carrier 1-Tb/s QAM Transmitter

Auteurs: F.Buchali
Publié dans: 2016
Éditeur: Pro OFC

Low-power inductorless RF receiver front-end with IIP2 calibration through body bias control in 28nm UTBB FDSOI

Auteurs: Dajana Danilovic, Vladimir Milovanovic, Andreia Cathelin, Andrei Vladimirescu, Borivoje Nikolic
Publié dans: 2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2016, Page(s) 87-90, ISBN 978-1-4673-8651-7
Éditeur: IEEE
DOI: 10.1109/RFIC.2016.7508257

A digital delay line with coarse/fine tuning through gate/body biasing in 28nm FDSOI

Auteurs: Ilias Sourikopoulos, Antoine Frappe, Andreia Cathelin, Laurent Clavier, Andreas Kaiser
Publié dans: ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 2016, Page(s) 145-148, ISBN 978-1-5090-2972-3
Éditeur: IEEE
DOI: 10.1109/ESSCIRC.2016.7598263

A 0.0175mm 2 600µW 32kHz input 307MHz output PLL with 190ps<inf>rms</inf> jitter in 28nm FD-SOI

Auteurs: Abhirup Lahiri, Nitin Gupta
Publié dans: ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 2016, Page(s) 339-342, ISBN 978-1-5090-2972-3
Éditeur: IEEE
DOI: 10.1109/ESSCIRC.2016.7598311

A digital sine-weighted switched-Gm mixer for single-clock power-scalable parallel receivers

Auteurs: Reda Kasri, Eric Klumperink, Philippe Cathelin, Eric Toumier, Bram Nauta
Publié dans: 2017 IEEE Custom Integrated Circuits Conference (CICC), 2017, Page(s) 1-4, ISBN 978-1-5090-5191-5
Éditeur: IEEE
DOI: 10.1109/CICC.2017.7993644

RF/analog and mixed-signal design techniques in FD-SOI technology

Auteurs: Andreia Cathelin
Publié dans: 2017 IEEE Custom Integrated Circuits Conference (CICC), 2017, Page(s) 1-53, ISBN 978-1-5090-5191-5
Éditeur: IEEE
DOI: 10.1109/CICC.2017.7993721

Class AB Base-Band Amplifier Design with Body Biasing in 28nm UTBB FD-SOI CMOS

Auteurs: Mirjana Videnovic-Misic
Publié dans: 2017
Éditeur: IEEE

“High Sigma Functional Qualification for Flipflops using MunEDA WiCkeD,”

Auteurs: N. Ben Salem, R.K. Gupta
Publié dans: 2017
Éditeur: MUGM 2017 (MunEDA Users Group Meeting)

Catalytic ALD of SiO2 as spacer for an E-Beam direct write self-aligned double patterning process on 300 mm wafers

Auteurs: K. Kühnel, S. Riedel, W. Weinreich, X. Thrun, M. Czernohorsky, B. Pätzold, M. Rudolph
Publié dans: 2016
Éditeur: 16th International Conference on Atomic Layer Deposition

Oxidation of Germanium at Low-temperature by Plasma Enhanced Processing

Auteurs: W. Lerch, N. Sacher, W. Kegel, J. Niess, M. Czernohorsky
Publié dans: 2016
Éditeur: 19th Workshop on Dielectrics in Microelectronic (WoDiM)

Cobalt MOCVD as a Flexible Process in Semiconductor Industry

Auteurs: L. Gerlich, M. Wislicenus, B. Uhlig, S. Riedel, R. Liske
Publié dans: 2016
Éditeur: Proc. Of Functional Integrated nanoSystems (nanoFIS 2016)

Selective Area Deposition of MOCVD Co for BEOL Capping Applications

Auteurs: M. Wislicenus, T. Martin, L. Gerlich, B. Uhlig
Publié dans: 2016
Éditeur: Proc. Of Area Selective Deposition Workshop (ASD 2016)

An in-depth analysis of temperature effect on DIBL in UTBB FD SOI MOSFETs based on experimental data, numerical simulations and analytical models

Auteurs: A.S.N. Pereira, G. de Streel, N. Planes, M. Haond, R. Giacomini, D. Flandre, V. Kilchytska
Publié dans: Solid-State Electronics, Numéro 128, 2017, Page(s) 67-71, ISSN 0038-1101
Éditeur: Pergamon Press Ltd.
DOI: 10.1016/j.sse.2016.10.017

High-K metal gate stacks with ultra-thin interfacial layers formed by low temperature microwave-based plasma oxidation

Auteurs: M. Czernohorsky, K. Seidel, K. Kühnel, J. Niess, N. Sacher, W. Kegel, W. Lerch
Publié dans: Microelectronic Engineering, Numéro 178, 2017, Page(s) 262-265, ISSN 0167-9317
Éditeur: Elsevier BV
DOI: 10.1016/j.mee.2017.05.041

In-line monitoring of strain distribution using high resolution X-ray Reciprocal space mapping into 20 nm SiGe pMOS

Auteurs: Aurèle Durand, Melissa Kaufling, Delphine Le-Cunff, Denis Rouchon, Patrice Gergaud
Publié dans: Materials Science in Semiconductor Processing, Numéro 70, 2017, Page(s) 99-104, ISSN 1369-8001
Éditeur: Pergamon Press
DOI: 10.1016/j.mssp.2016.12.003

Benefits of XPS nanocharacterization for process development and industrial control of thin SiGe channel layers in advanced CMOS technologies

Auteurs: L. Fauquier, B. Pelissier, D. Jalabert, F. Pierre, J.M. Hartmann, F. Rozé, D. Doloy, D. Le Cunff, C. Beitia, T. Baron
Publié dans: Materials Science in Semiconductor Processing, Numéro 70, 2017, Page(s) 105-110, ISSN 1369-8001
Éditeur: Pergamon Press
DOI: 10.1016/j.mssp.2016.10.028

Strain mapping of semiconductor specimens with nm-scale resolution in a transmission electron microscope

Auteurs: David Cooper, Thibaud Denneulin, Nicolas Bernier, Armand Béché, Jean-Luc Rouvière
Publié dans: Micron, Numéro 80, 2016, Page(s) 145-165, ISSN 0968-4328
Éditeur: Pergamon Press Ltd.
DOI: 10.1016/j.micron.2015.09.001

Using Electron Diffraction Techniques, CBED and N-PED to measure Strain with High Precision and High Spatial Resolution

Auteurs: J.L. Rouviere, Y. Martin, N. Bernier, M. Vigouroux, D. Cooper, J.M. Zuo
Publié dans: Microscopy and Microanalysis, Numéro 21/S3, 2015, Page(s) 2209-2210, ISSN 1431-9276
Éditeur: Cambridge University Press
DOI: 10.1017/S1431927615011824

Nanoscale Strain Mapping in Embedded SiGe Devices by Dual Lens Dark Field Electron Holography and Precession Electron Diffraction

Auteurs: Y. Y. Wang, D. Cooper, J. Rouviere, C.E. Murray, N. Bernier, J. Bruley
Publié dans: Microscopy and Microanalysis, Numéro 21/S3, 2015, Page(s) 1963-1964, ISSN 1431-9276
Éditeur: Cambridge University Press
DOI: 10.1017/S1431927615010594

Combining 2 nm Spatial Resolution and 0.02% Precision for Deformation Mapping of Semiconductor Specimens in a Transmission Electron Microscope by Precession Electron Diffraction

Auteurs: David Cooper, Nicolas Bernier, Jean-Luc Rouvière
Publié dans: Nano Letters, Numéro 15/8, 2015, Page(s) 5289-5294, ISSN 1530-6984
Éditeur: American Chemical Society
DOI: 10.1021/acs.nanolett.5b01614

Strain mapping at the nanoscale using precession electron diffraction in transmission electron microscope with off axis camera

Auteurs: M. P. Vigouroux, V. Delaye, N. Bernier, R. Cipro, D. Lafond, G. Audoit, T. Baron, J. L. Rouvière, M. Martin, B. Chenevier, F. Bertin
Publié dans: Applied Physics Letters, Numéro 105/19, 2014, Page(s) 191906, ISSN 0003-6951
Éditeur: American Institute of Physics
DOI: 10.1063/1.4901435

Characterization and modelling of layout effects in SiGe channel pMOSFETs from 14nm UTBB FDSOI technology

Auteurs: R. Berthelon, F. Andrieu, S. Ortolland, R. Nicolas, T. Poiroux, E. Baylac, D. Dutartre, E. Josse, A. Claverie, M. Haond
Publié dans: Solid-State Electronics, Numéro 128, 2017, Page(s) 72-79, ISSN 0038-1101
Éditeur: Pergamon Press Ltd.
DOI: 10.1016/j.sse.2016.10.011

Implementation of Band-to-Band Tunneling Phenomena in a Multisubband Ensemble Monte Carlo Simulator: Application to Silicon TFETs

Auteurs: Cristina Medina-Bailon, Jose L. Padilla, Carlos Sampedro, Cem Alper, Francisco Gamiz, Adrian Mihai Ionescu
Publié dans: IEEE Transactions on Electron Devices, Numéro 64/8, 2017, Page(s) 3084-3091, ISSN 0018-9383
Éditeur: Institute of Electrical and Electronics Engineers
DOI: 10.1109/TED.2017.2715403

Insights on the Body Charging and Noise Generation by Impact Ionization in Fully Depleted SOI MOSFETs

Auteurs: Carlos Marquez, Noel Rodriguez, Francisco Gamiz, Akiko Ohata
Publié dans: IEEE Transactions on Electron Devices, Numéro 64/12, 2017, Page(s) 5093-5098, ISSN 0018-9383
Éditeur: Institute of Electrical and Electronics Engineers
DOI: 10.1109/TED.2017.2762733

Systematic method for electrical characterization of random telegraph noise in MOSFETs

Auteurs: Carlos Marquez, Noel Rodriguez, Francisco Gamiz, Akiko Ohata
Publié dans: Solid-State Electronics, Numéro 128, 2017, Page(s) 115-120, ISSN 0038-1101
Éditeur: Pergamon Press Ltd.
DOI: 10.1016/j.sse.2016.10.031

The Measurement of Strain, Chemistry and Electric Fields by STEM based Techniques

Auteurs: J.-L. Rouviere, B. Haas, E. Robin, D. Cooper, N. Bernier, M. Williamson
Publié dans: Microscopy and Microanalysis, Numéro 23/S1, 2017, Page(s) 1414-1415, ISSN 1431-9276
Éditeur: Cambridge University Press
DOI: 10.1017/S1431927617007735

300 mm SiGe-On-Insulator Substrates with High Ge Content (70%) Fabricated Using the Smart Cut Technology

Auteurs: J. Widiez, C. Veytizou, J.-M. Hartmann, V. Loup, P. Besson, N. Baumel, C. Figuet, I. Huyet, F. Mazen, W. Schwarzenbach, C. Tempesta, L. Ecarnot
Publié dans: ECS Transactions, Numéro 75/8, 2016, Page(s) 79-88, ISSN 1938-5862
Éditeur: Electrochemical Society, Inc.
DOI: 10.1149/07508.0079ecst

Out-of-equilibrium body potential measurements in pseudo-MOSFET for sensing applications

Auteurs: Licinius Benea, Maryline Bawedin, Cécile Delacour, Irina Ionica
Publié dans: Solid-State Electronics, 2017, ISSN 0038-1101
Éditeur: Pergamon Press Ltd.
DOI: 10.1016/j.sse.2017.11.010

(Invited) Epitaxial Growth of Low Defect SiGe Buffer Layers for Integration of New Materials on 300 mm Silicon Wafers

Auteurs: G. Kozlowski, O. Fursenko, P. Zaumseil, T. Schroeder, M. Vorderwestner, P. Storck
Publié dans: ECS Transactions, Numéro 50/9, 2013, Page(s) 613-621, ISSN 1938-5862
Éditeur: Electrochemical Society, Inc.
DOI: 10.1149/05009.0613ecst

Ultra-thin body & buried oxide SOI substrate development and qualification for Fully Depleted SOI device with back bias capability

Auteurs: Walter Schwarzenbach, Bich-Yen Nguyen, Frederic Allibert, Christophe Girard, Christophe Maleville
Publié dans: Solid-State Electronics, Numéro 117, 2016, Page(s) 2-9, ISSN 0038-1101
Éditeur: Pergamon Press Ltd.
DOI: 10.1016/j.sse.2015.11.008

(Invited) Low-Temperature Microwave-Based Plasma Oxidation of Ge and Oxidation of Silicon Followed by Plasma Nitridation

Auteurs: W. Lerch, T. Schick, N. Sacher, W. Kegel, J. Niess, M. Czernohorsky, S. Riedel
Publié dans: ECS Transactions, Numéro 72/4, 2016, Page(s) 101-114, ISSN 1938-5862
Éditeur: Electrochemical Society, Inc.
DOI: 10.1149/07204.0101ecst

Impact of non uniform strain configuration on transport properties for FD14+ devices

Auteurs: C. Medina-Bailon, C. Sampedro, F. Gámiz, A. Godoy, L. Donetti
Publié dans: Solid-State Electronics, Numéro 115, 2016, Page(s) 232-236, ISSN 0038-1101
Éditeur: Pergamon Press Ltd.
DOI: 10.1016/j.sse.2015.08.013

Direct Characterization of Impact Ionization Current in Silicon-on-Insulator Body-Contacted MOSFETs

Auteurs: C. Marquez, N. Rodriguez, J. M. Montes, R. Ruiz, F. Gamiz, C. Sampedro, A. Ohata
Publié dans: ECS Transactions, Numéro 66/5, 2015, Page(s) 93-99, ISSN 1938-5862
Éditeur: Electrochemical Society, Inc.
DOI: 10.1149/06605.0093ecst

Electrical characterization of Random Telegraph Noise in Fully-Depleted Silicon-On-Insulator MOSFETs under extended temperature range and back-bias operation

Auteurs: Carlos Marquez, Noel Rodriguez, Francisco Gamiz, Rafael Ruiz, Akiko Ohata
Publié dans: Solid-State Electronics, Numéro 117, 2016, Page(s) 60-65, ISSN 0038-1101
Éditeur: Pergamon Press Ltd.
DOI: 10.1016/j.sse.2015.11.022

SleepTalker: A ULV 802.15.4a IR-UWB Transmitter SoC in 28-nm FDSOI Achieving 14 pJ/b at 27 Mb/s With Channel Selection Based on Adaptive FBB and Digitally Programmable Pulse Shaping

Auteurs: Guerric de Streel, Francois Stas, Thibaut Gurne, Francois Durant, Charlotte Frenkel, Andreia Cathelin, David Bol
Publié dans: IEEE Journal of Solid-State Circuits, Numéro 52/4, 2017, Page(s) 1163-1177, ISSN 0018-9200
Éditeur: Institute of Electrical and Electronics Engineers
DOI: 10.1109/JSSC.2016.2645607

Fully Depleted Silicon on Insulator Devices CMOS: The 28-nm Node Is the Perfect Technology for Analog, RF, mmW, and Mixed-Signal System-on-Chip Integration

Auteurs: Andreia Cathelin
Publié dans: IEEE Solid-State Circuits Magazine, Numéro 9/4, 2017, Page(s) 18-26, ISSN 1943-0582
Éditeur: Institute of Electrical and Electronics Engineers
DOI: 10.1109/MSSC.2017.2745738

All Operation Region Characterization and Modeling of Drain and Gate Current Mismatch in 14-nm Fully Depleted SOI MOSFETs

Auteurs: Theano A. Karatsori, Christoforos G. Theodorou, Emmanuel Josse, Charalabos A. Dimitriadis, G. Ghibaudo
Publié dans: IEEE Transactions on Electron Devices, Numéro 64/5, 2017, Page(s) 2080-2085, ISSN 0018-9383
Éditeur: Institute of Electrical and Electronics Engineers
DOI: 10.1109/TED.2017.2686381

Study of Hot-Carrier-Induced Traps in Nanoscale UTBB FD-SOI MOSFETs by Low-Frequency Noise Measurements

Auteurs: Theano A. Karatsori, Christoforos G. Theodorou, Xavier Mescot, Sebastien Haendler, Nicolas Planes, Gerard Ghibaudo, Charalabos A. Dimitriadis
Publié dans: IEEE Transactions on Electron Devices, 2016, Page(s) 1-7, ISSN 0018-9383
Éditeur: Institute of Electrical and Electronics Engineers
DOI: 10.1109/TED.2016.2583504

Characterization and industrial control of local stress in microelectronics: - Applications to advanced transistors technology of 20 nm

Auteurs: A.Durand
Publié dans: 2016
Éditeur: School of PhD Grenoble

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