The EXTRA reconfigurable platform has been defined and studies have been performed on the analysis of the trade-offs in reconfiguration granularity, on the optimal off-loading to FPGA accelerators and on the system design exploration. Concurrently, we have developed Computer-Aided Design (CAD) tools to support the efficient use of the reconfigurable architecture platform. A tools frontend was designed within the CaaS (CAD-as-a-Service) concept and we have extended it with all the necessary tools to provide the entire design flow for reconfigurable systems. Our tools platform is called CAOS (CAD as an Adaptive OpenPlatform Service). The focus in the first project half has been on new research aspects needed for CAOS: polyhedral analysis and transformation, development of application analytical models and estimation of HW implementations, HW/SW Co-design for exascale reconfigurable computing, and integration and extension of vendor tools.
We have advertised our initial platform to the research community through a leaflet which was distributed at major conferences and exhibitions and through numerous presentations at workshops and conferences within the research domain. The goal is to convince other researchers to use our platform to enable research on tools for reconfigurable hardware design, on reconfigurable applications and on reconfigurable architectures. Of course, the EXTRA project partners also plan to use our platform to extend the state-of-the-art in reconfigurable HPC computing.
On the tools front, we have improved the configuration representation to enable just-in-time synthesis, we have analyzed the relations between synthesis, mapping, and placement and routing (P&R) tools as a first step to optimize the joint performance of these tools, and we have shown the advantages of using Virtual Coarse Grained Reconfigurable Arrays (VCGRAs) to provide a faster synthesis based on a hierarchical multi-level approach. We also started work on hardware monitoring and emergency management and the addition of hardware debugging tools to the framework.
On the applications front, we have focused on optimizations of the three EXTRA applications, on analyzing and detecting reconfiguration opportunities in these applications, and on the first implementations of reconfigurable functions and structures in reconfigurable devices.
Finally, on the reconfigurable architecture front, we have started to develop techniques and guidelines that improve the potential of reconfigurable technology, with a first focus on investigations of the optimal reconfiguration infrastructure, which will be integrated into the final project platform, on the development of tools that support on-chip configuration generation, and on the exploration of the interfaces between the heterogeneous parts of the final EXTRA platform.
We are currently finalizing the initial demonstrators, which will be shown on the project review.
