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Exploiting eXascale Technology with Reconfigurable Architectures

Objective

To handle the stringent performance requirements of future exascale High Performance Computing (HPC) applications, HPC systems need ultra-efficient heterogeneous compute nodes. To reduce power and increase performance, such compute nodes will require reconfiguration as an intrinsic feature, so that specific HPC application features can be optimally accelerated at all times, even if they regularly change over time.
In the EXTRA project, we create a new and flexible exploration platform for developing reconfigurable architectures, design tools and HPC applications with run-time reconfiguration built-in from the start. The idea is to enable the efficient co-design and joint optimization of architecture, tools, applications, and reconfiguration technology in order to prepare for the necessary HPC hardware nodes of the future.
The project EXTRA covers the complete chain from architecture up to the application:
• More coarse-grain reconfigurable architectures that allow reconfiguration on higher functionality levels and therefore provide much faster reconfiguration than at the bit level.
• The development of just-in time synthesis tools that are optimized for fast (but still efficient) re-synthesis of application phases to new, specialized implementations through reconfiguration.
• The optimization of applications that maximally exploit reconfiguration.
• Suggestions for improvements to reconfigurable technologies to enable the proposed reconfiguration of the architectures.
In conclusion, EXTRA focuses on the fundamental building blocks for run-time reconfigurable exascale HPC systems: new reconfigurable architectures with very low reconfiguration overhead, new tools that truly take reconfiguration as a design concept, and applications that are tuned to maximally exploit run-time reconfiguration techniques.
Our goal is to provide the European platform for run-time reconfiguration to maintain Europe’s competitive edge and leadership in run-time reconfigurable computing.

Call for proposal

H2020-FETHPC-2014
See other projects for this call

Funding Scheme

RIA - Research and Innovation action

Coordinator

UNIVERSITEIT GENT
Address
Sint Pietersnieuwstraat 25
9000 Gent
Belgium
Activity type
Higher or Secondary Education Establishments
EU contribution
€ 530 296

Participants (8)

EREVNITIKO PANEPISTIMIAKO INSTITOUTO TILEPIKONONIAKON SYSTIMATON
Greece
EU contribution
€ 420 000
Address
Kounoupidiana Akrotirio Tuc Campus
73100 Chania
Activity type
Research Organisations
IMPERIAL COLLEGE OF SCIENCE TECHNOLOGY AND MEDICINE
United Kingdom
EU contribution
€ 559 080
Address
South Kensington Campus Exhibition Road
SW7 2AZ London
Activity type
Higher or Secondary Education Establishments
POLITECNICO DI MILANO
Italy
EU contribution
€ 451 250
Address
Piazza Leonardo Da Vinci 32
20133 Milano
Activity type
Higher or Secondary Education Establishments
UNIVERSITEIT VAN AMSTERDAM
Netherlands
EU contribution
€ 533 836
Address
Spui 21
1012WX Amsterdam
Activity type
Higher or Secondary Education Establishments
RUHR-UNIVERSITAET BOCHUM
Germany
EU contribution
€ 476 250
Address
Universitaetsstrasse 150
44801 Bochum
Activity type
Higher or Secondary Education Establishments
MAXELER TECHNOLOGIES LIMITED
United Kingdom
EU contribution
€ 415 000
Address
3 & 4 Albion Place
W6 0QT London
Activity type
Private for-profit entities (excluding Higher or Secondary Education Establishments)
SYNELIXIS LYSEIS PLIROFORIKIS AUTOMATISMOU & TILEPIKOINONION ANONIMI ETAIRIA
Greece
EU contribution
€ 305 812,50
Address
Farmakidou 10
34100 Chalkida
Activity type
Private for-profit entities (excluding Higher or Secondary Education Establishments)
THE CHANCELLOR MASTERS AND SCHOLARSOF THE UNIVERSITY OF CAMBRIDGE
United Kingdom
EU contribution
€ 298 406
Address
Trinity Lane The Old Schools
CB2 1TN Cambridge
Activity type
Higher or Secondary Education Establishments