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Exploiting eXascale Technology with Reconfigurable Architectures

Deliverables

Project Handbook, e-mail reflector, web site and FTP site

Writing of the project Handbook, setting up an e-mail reflector, web site and FTP site.

Publications

Optimizing streaming stencil time-step designs via FPGA floorplanning

Author(s): Marco Rabozzi, Giuseppe Natale, Biagio Festa, Antonio Miele, Marco D. Santambrogio
Published in: 2017 27th International Conference on Field Programmable Logic and Applications (FPL), 2017, Page(s) 1-4
DOI: 10.23919/FPL.2017.8056764

FPGA-based PairHMM Forward Algorithm for DNA Variant Calling

Author(s): Davide Sampietro, Chiara Crippa, Lorenzo Di Tucci, Emanuele Del Sozzo, Marco D. Santambrogio
Published in: 2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2018, Page(s) 1-8
DOI: 10.1109/ASAP.2018.8445119

Heterogeneous exascale supercomputing: The role of CAD in the exaFPGA project

Author(s): M. Rabozzi, G. Natale, E. Del Sozzo, A. Scolari, L. Stornaiuolo, M. D. Santambrogio
Published in: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, 2017, Page(s) 410-415
DOI: 10.23919/DATE.2017.7927025

CGRA Tool Flow for Fast Run-Time Reconfiguration

Author(s): Florian Fricke, André Werner, Keyvan Shahin, Michael Huebner
Published in: Proc. of the 14th International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), 2018, Page(s) 661-672
DOI: 10.1007/978-3-319-78890-6_53

Superimposed in-circuit debugging for self-healing FPGA overlays

Author(s): Alexandra Kourfali, Dirk Stroobandt
Published in: 2018 IEEE 19th Latin-American Test Symposium (LATS), 2018, Page(s) 1-6
DOI: 10.1109/LATW.2018.8349688

Tool flow for automatic generation of architectures and test-cases to enable the evaluation of CGRAs in the context of HPC applications

Author(s): Florian Fricke, Andre Werner, Michael Hubner
Published in: 2017 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2017, Page(s) 1-2
DOI: 10.1109/DASIP.2017.8122124

Hardware Compilation of Deep Neural Networks: An Overview

Author(s): Ruizhe Zhao, Shuanglong Liu, Ho-Cheung Ng, Erwei Wang, James J. Davis, Xinyu Niu, Xiwei Wang, Huifeng Shi, George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
Published in: 2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2018, Page(s) 1-8
DOI: 10.1109/ASAP.2018.8445088

SICTA: A superimposed in-circuit fault tolerant architecture for SRAM-based FPGAs

Author(s): Alexandra Kourfali, Amit Kulkarni, Dirk Stroobandt
Published in: 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS), 2017, Page(s) 5-8
DOI: 10.1109/IOLTS.2017.8046168

ADAM - Automated Design Analysis and Merging for Speeding up FPGA Development

Author(s): Ho-Cheung Ng, Shuanglong Liu, Wayne Luk
Published in: Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays - FPGA '18, 2018, Page(s) 189-198
DOI: 10.1145/3174243.3174247

Hierarchical force-based block spreading for analytical FPGA placement

Author(s): Dries Vercruyce, Elias Vansteenkiste, Dirk Stroobandt
Published in: FPL 2018, 2018

The Role of CAD Frameworks in Heterogeneous FPGA-Based Cloud Systems

Author(s): Lorenzo Di Tucci, Marco Rabozzi, Luca Stornaiuolo, Marco D. Santambrogio
Published in: 2017 IEEE International Conference on Computer Design (ICCD), 2017, Page(s) 423-426
DOI: 10.1109/ICCD.2017.74

CRRS: Custom Regression and Regularisation Solver for Large-scale Linear Systems,

Author(s): A.-I. Cross, L. Guo, W. Luk and M. Salmon
Published in: International Conference on Field-Programmable Logic and Applications, 2018

A NoC-based custom FPGA configuration memory architecture for ultra-fast micro-reconfiguration

Author(s): Amit Kulkarni, Poona Bahrebar, Dirk Stroobandt, Giulio Stramondo, Catalin Bogdan Ciobanu, Ana Lucia Varbanescu
Published in: 2017 International Conference on Field Programmable Technology (ICFPT), 2017, Page(s) 203-206
DOI: 10.1109/FPT.2017.8280141

An open reconfigurable research platform as stepping stone to exascale high-performance computing

Author(s): Dirk Stroobandt, Catalin Bogdan Ciobanu, Marco D. Santambrogio, Gabriel Figueiredo, Andreas Brokalakis, Dionisios Pnevmatikatos, Michael Huebner, Tobias Becker, Alex J. W. Thom
Published in: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, 2017, Page(s) 416-421
DOI: 10.23919/DATE.2017.7927026

Towards Application-Centric Parallel Memories

Author(s): Giulio Stramondo, Catalin Bogdan Ciobanu, Ana Lucia Varbanescu and Cees De Laat
Published in: EuroPar Workshops 2018 -- HeteroPar'18, 2018

From Tensor Algebra to Hardware Accelerators: Generating Streaming Architectures for Solving Partial Differential Equations

Author(s): Francis P. Russell, James Stanley Targett, Wayne Luk
Published in: 2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2018, Page(s) 1-8
DOI: 10.1109/ASAP.2018.8445093

A Parallel, Energy Efficient Hardware Architecture for the merAligner on FPGA Using Chisel HCL

Author(s): Lorenzo Di Tucci, Davide Conficconi, Alessandro Comodi, Steven Hofmeyr, David Donofrio, Marco D. Santambrogio
Published in: 2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2018, Page(s) 214-217
DOI: 10.1109/IPDPSW.2018.00041

In-Circuit FPGA Debugging using Parameterised Reconfigurations

Author(s): Alexandra Kourfali and Dirk Stroobandt
Published in: 54th ACM/ESDA/IEEE Design Automation Conference (DAC), 2017

Superimposed In-Circuit Fault Mitigation for Dynamically Reconfigurable FPGAs

Author(s): Alexandra Kourfali, David Merodio Codinachs and Dirk Stroobandt
Published in: IEEE Conference on Radiation Effects on Components and Systems (RADECS), 2017

An FPGA-Based Acceleration Methodology and Performance Model for Iterative Stencils

Author(s): Enrico Reggiani, Giuseppe Natale, Carlo Moroni, Marco D. Santambrogio
Published in: 2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2018, Page(s) 115-122
DOI: 10.1109/IPDPSW.2018.00026

Towards Hardware Accelerated Reinforcement Learning for Application-Specific Robotic Control

Author(s): Shengjia Shao, Jason Tsai, Michal Mysior, Wayne Luk, Thomas Chau, Alexander Warren, Ben Jeppesen
Published in: 2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2018, Page(s) 1-8
DOI: 10.1109/ASAP.2018.8445099

From exaflop to exaflow

Author(s): Tobias Becker, Pavel Burovskiy, Anna Maria Nestorov, Hristina Palikareva, Enrico Reggiani, Georgi Gaydadjiev
Published in: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, 2017, Page(s) 404-409
DOI: 10.23919/DATE.2017.7927024

MAX-PolyMem: High-Bandwidth Polymorphic Parallel Memories for DFEs

Author(s): Catalin Bogdan Ciobanu, Giulio Stramondo, Cees de Laat, Ana Lucia Varbanescu
Published in: 2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2018, Page(s) 107-114
DOI: 10.1109/IPDPSW.2018.00025

Towards Efficient Convolutional Neural Network for Domain-Specific Applications on FPGA

Author(s): R. Zhao, H.C. Ng, W. Luk and X. Niu
Published in: International Conference on Field-Programmable Logic and Applications, 2018

HLS Support for Polymorphic Parallel Memories

Author(s): Luca Stornaiuolo, Marco Rabozzi, Marco D. Santambrogio, Donatella Sciuto, Giulio Stramondo, Catalin Bogdan Ciobanu, Ana Lucia Varbanescu
Published in: proceeding of the 26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2018

OXiGen: A Tool for Automatic Acceleration of C Functions Into Dataflow FPGA-Based Kernels

Author(s): Francesco Peverelli, Marco Rabozzi, Emanuele Del Sozzo, Marco D. Santambrogio
Published in: 2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2018, Page(s) 91-98
DOI: 10.1109/IPDPSW.2018.00023

Accelerated Inference of Positive Selection on Whole Genomes

Author(s): Nikolaos Alachiotis, Charalampos Vatsolakis, Grigorios Chrysos and Dionisios N. Pnevmatikatos
Published in: International Conference on Field-Programmable Logic and Applications, 2018

A CAD Open Platform for High Performance Reconfigurable Systems in the EXTRA Project

Author(s): Marco Rabozzi, Rolando Brondolin, Giuseppe Natale, Emanuele Del Sozzo, Michael Huebner, Andreas Brokalakis, Catalin Ciobanu, Dirk Stroobandt, Marco Domenico Santambrogio
Published in: 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2017, Page(s) 368-373
DOI: 10.1109/ISVLSI.2017.71

Liquid: High quality scalable placement for large heterogeneous FPGAs

Author(s): Dries Vercruyce, Elias Vansteenkiste, Dirk Stroobandt
Published in: 2017 International Conference on Field Programmable Technology (ICFPT), 2017, Page(s) 17-24
DOI: 10.1109/FPT.2017.8280116

A Scalable FPGA Design for Cloud N-Body Simulation

Author(s): Emanuele Del Sozzo, Marco Rabozzi, Lorenzo Di Tucci, Donatella Sciuto, Marco D. Santambrogio
Published in: 2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2018, Page(s) 1-8
DOI: 10.1109/ASAP.2018.8445106

EXTRA: An Open Platform for Reconfigurable Architectures

Author(s): Catalin Bogdan Ciobanu, Giulio Stramondo, Ana Lucia Varbanescu, Andreas Brokalakis, Antonis Nikitakis, Lorenzo Di Tucci, Marco Rabozzi, Luca Stornaiuolo, Marco D. Santambrogio, Grigorios Chrysos, Charalampos Vatsolakis, Charitopoulos Georgios, Dionisios Pnevmatikatos
Published in: Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XVIII), 2018 International Conference on, 2018
DOI: 10.1145/3229631.3236092

A generic high throughput architecture for stream processing

Author(s): Christes Rousopoulos, Ektoras Karandeinos, Grigorios Chrysos, Apostolos Dollas, Dionisios N. Pnevmatikatos
Published in: 2017 27th International Conference on Field Programmable Logic and Applications (FPL), 2017, Page(s) 1-5
DOI: 10.23919/FPL.2017.8056796

Five-point algorithm: An efficient cloud-based FPGA implementation

Author(s): Marco Rabozzi, Emanuele Del Sozzo, Lorenzo Di Tucci, Marco D. Santambrogio
Published in: 2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2018, Page(s) 1-8
DOI: 10.1109/ASAP.2018.8445097

A decoupled access-execute architecture for reconfigurable accelerators

Author(s): George Charitopoulos, Charalampos Vatsolakis, Grigorios Chrysos, Dionisios N. Pnevmatikatos
Published in: Proceedings of the 15th ACM International Conference on Computing Frontiers - CF '18, 2018, Page(s) 244-247
DOI: 10.1145/3203217.3203267

Online reconfigurable routing method for handling link failures in NoC-based MPSoCs

Author(s): Poona Bahrebar, Dirk Stroobandt
Published in: 2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2016, Page(s) 1-8
DOI: 10.1109/ReCoSoC.2016.7533905

Runtime-quality tradeoff in partitioning based multithreaded packing

Author(s): Dries Vercruyce, Elias Vansteenkiste, Dirk Stroobandt
Published in: 2016 26th International Conference on Field Programmable Logic and Applications (FPL), 2016, Page(s) 1-9
DOI: 10.1109/FPL.2016.7577300

Efficient Hardware Debugging Using Parameterized FPGA Reconfiguration

Author(s): Alexandra Kourfali, Dirk Stroobandt
Published in: 2016 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2016, Page(s) 277-282
DOI: 10.1109/IPDPSW.2016.95

A 16-Bit Reconfigurable Encryption Processor for p-Cipher

Author(s): Mohamed El-Hadedy, Hristina Mihajloska, Danilo Gligoroski, Amit Kulkarni, Dirk Stroobandt, Kevin Skadron
Published in: 2016 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2016, Page(s) 162-171
DOI: 10.1109/IPDPSW.2016.27

MiCAP: a custom reconfiguration controller for dynamic circuit specialization

Author(s): Amit Kulkarni, Vipin Kizheppatt, Dirk Stroobandt
Published in: 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2015, Page(s) 1-6
DOI: 10.1109/ReConFig.2015.7393327

Hardware Design Automation of Convolutional Neural Networks

Author(s): Andrea Solazzo, Emanuele Del Sozzo, Irene De Rose, Matteo De Silvestri, Gianluca C. Durelli, Marco D. Santambrogio
Published in: 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2016, Page(s) 224-229
DOI: 10.1109/ISVLSI.2016.101

Pixie: A heterogeneous Virtual Coarse-Grained Reconfigurable Array for high performance image processing applications

Author(s): A. Kulkarni, A. Werner, F. Fricke, D. Stroobandt and M. Huebner
Published in: 3rd International Workshop on Overlay Architectures for FPGAs (OLAF2017), 2017

EXTRA: Towards the exploitation of eXascale technology for reconfigurable architectures

Author(s): Dirk Stroobandt, Ana Lucia Varbanescu, Catalin Bogdan Ciobanu, Muhammed Al Kadi, Andreas Brokalakis, George Charitopoulos, Tim Todman, Xinyu Niu, Dionisios Pnevmatikatos, Amit Kulkarni, Elias Vansteenkiste, Wayne Luk, Marco D. Santambrogio, Donatella Sciuto, Michael Huebner, Tobias Becker, Georgi Gaydadjiev, Antonis Nikitakis, Alex J. W. Thom
Published in: 2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2016, Page(s) 1-7
DOI: 10.1109/ReCoSoC.2016.7533896

An FPGA-based high-throughput stream join architecture

Author(s): Charalabos Kritikakis, Grigorios Chrysos, Apostolos Dollas, Dionisios N. Pnevmatikatos
Published in: 2016 26th International Conference on Field Programmable Logic and Applications (FPL), 2016, Page(s) 1-4
DOI: 10.1109/FPL.2016.7577354

Design and exploration of routing methods for NoC-based multicore systems

Author(s): Poona Bahrebar, Dirk Stroobandt
Published in: 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2015, Page(s) 1-4
DOI: 10.1109/ReConFig.2015.7393296

EXTRA: Towards an Efficient Open Platform for Reconfigurable High Performance Computing

Author(s): Catalin Bogdan Ciobanu, Ana Lucia Varbanescu, Dionisios Pnevmatikatos, George Charitopoulos, Xinyu Niu, Wayne Luk, Marco D. Santambrogio, Donatella Sciuto, Muhammed Al Kadi, Michael Huebner, Tobias Becker, Georgi Gaydadjiev, Andreas Brokalakis, Antonis Nikitakis, Alex J. W. Thom, Elias Vansteenkiste, Dirk Stroobandt
Published in: 2015 IEEE 18th International Conference on Computational Science and Engineering, 2015, Page(s) 339-342
DOI: 10.1109/CSE.2015.54

A Fully Parameterized Virtual Coarse Grained Reconfigurable Array for High Performance Computing Applications

Author(s): Amit Kulkarni, Elias Vasteenkiste, Dirk Stroobandt, Andreas Brokalakis, Antonios Nikitakis
Published in: 2016 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2016, Page(s) 265-270
DOI: 10.1109/IPDPSW.2016.13

A polyhedral model-based framework for dataflow implementation on FPGA devices of iterative stencil loops

Author(s): Giuseppe Natale, Giulio Stramondo, Pietro Bressana, Riccardo Cattaneo, Donatella Sciuto, Marco D. Santambrogio
Published in: Proceedings of the 35th International Conference on Computer-Aided Design - ICCAD '16, 2016, Page(s) 1-8
DOI: 10.1145/2966986.2966995

Heterogeneous exascale supercomputing: the role of CAD in the exaFPGA project

Author(s): M. Rabozzi, G. Natale, E. Del Sozzo, A. Scolari, L. Stornaiuolo, and M. D. Santambrogio
Published in: 2017 Design, Automation Test in Europe Conference Exhibition (DATE), 2017

On the Automation of High Level Synthesis of Convolutional Neural Networks

Author(s): Emanuele Del Sozzo, Andrea Solazzo, Antonio Miele, Marco D. Santambrogio
Published in: 2016 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2016, Page(s) 217-224
DOI: 10.1109/IPDPSW.2016.153

Towards a Performance-Aware Power Capping Orchestrator for the Xen Hypervisor

Author(s): M. Arnaboldi, M. Ferroni, M. D. Santambrogio
Published in: Embed With Linux (EWiLi) Workshop 2016, 2016

ProFAX: A hardware acceleration of a protein folding algorithm

Author(s): Giulia Guidi, Lorenzo Di Tucci, Marco D. Santambrogio
Published in: 2016 IEEE 2nd International Forum on Research and Technologies for Society and Industry Leveraging a better tomorrow (RTSI), 2016, Page(s) 1-6
DOI: 10.1109/RTSI.2016.7740584

Knowledge Transfer in Automatic Optimisation of Reconfigurable Designs

Author(s): Maciej Kurek, Marc Peter Deisenroth, Wayne Luk, Timothy Todman
Published in: 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2016, Page(s) 84-87
DOI: 10.1109/FCCM.2016.29

EURECA compilation: Automatic optimisation of cycle-reconfigurable circuits

Author(s): Xinyu Niu, Nicholas Ng, Tomofumi Yuki, Shaojun Wang, Nobuko Yoshida, Wayne Luk
Published in: 2016 26th International Conference on Field Programmable Logic and Applications (FPL), 2016, Page(s) 1-4
DOI: 10.1109/FPL.2016.7577359

F-CNN: An FPGA-based framework for training Convolutional Neural Networks

Author(s): Wenlai Zhao, Haohuan Fu, Wayne Luk, Teng Yu, Shaojun Wang, Bo Feng, Yuchun Ma, Guangwen Yang
Published in: 2016 IEEE 27th International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2016, Page(s) 107-114
DOI: 10.1109/ASAP.2016.7760779

A Domain Specific Language for accelerated Multilevel Monte Carlo simulations

Author(s): Ben Lindsey, Matthew Leslie, Wayne Luk
Published in: 2016 IEEE 27th International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2016, Page(s) 99-106
DOI: 10.1109/ASAP.2016.7760778

A Scalable Dataflow Accelerator for Real Time Onboard Hyperspectral Image Classification

Author(s): Shaojun Wang, Xinyu Niu, Ning Ma, Wayne Luk, Philip Leong, Yu Peng
Published in: Part of the Lecture Notes in Computer Science book series (LNCS, volume 9625), 2016, Page(s) 105-116
DOI: 10.1007/978-3-319-30481-6_9

Connect on the fly: Enhancing and prototyping of cycle-reconfigurable modules

Author(s): Hao Zhou, Xinyu Niu, Junqi Yuan, Lingli Wang, Wayne Luk
Published in: 2016 26th International Conference on Field Programmable Logic and Applications (FPL), 2016, Page(s) 1-8
DOI: 10.1109/FPL.2016.7577332

Optimising Sparse Matrix Vector multiplication for large scale FEM problems on FPGA

Author(s): Paul Grigoras, Pavel Burovskiy, Wayne Luk, Spencer Sherwin
Published in: 2016 26th International Conference on Field Programmable Logic and Applications (FPL), 2016, Page(s) 1-9
DOI: 10.1109/FPL.2016.7577352

CASK - Open-Source Custom Architectures for Sparse Kernels

Author(s): Paul Grigoras, Pavel Burovskiy, Wayne Luk
Published in: Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays - FPGA '16, 2016, Page(s) 179-184
DOI: 10.1145/2847263.2847338

A Decoupled Access-Execute Architecture for Reconfigurable Accelerators

Author(s): George Charitopoulos, Charalampos Vatsolakis, Stefanos Sidiropoulos, Grigorios Chrysos and Dionisios Pnevmatikatos
Published in: 11th HiPEAC Workshop on Reconfigurable Computing (WRC'2017), 2017

Customizable Memory Systems for High Performance Reconfigurable Architectures

Author(s): Catalin Ciobanu, Giulio Stramondo, Ana Lucia Varbanescu
Published in: International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded (ACACES) 2016, 2016

A Scalable Dataflow Implementation of Curran’s Approximation Algorithm

Author(s): Anna Maria Nestorov, Enrico Reggiani, Marco Domenico Santambrogio, Pavel Burovskiy, Hristina Palikareva and Tobias Becker
Published in: Reconfigurable Architectures Workshop, 2017

From exaflop to exaflow

Author(s): • Tobias Becker, Pavel Burovskiy, Anna Maria Nestorov, Hristina Palikareva, Enrico Reggiani, Georgi Gaydadjiev
Published in: Proceedings of the Design Automation and Test in Europe Conference, 2017

How effective are custom parallel memories

Author(s): Giulio Stramondo, Ana Lucia Varbanescu and Catalin Bogdan Ciobanu
Published in: ICT.Open, 2017

The Case for Custom Parallel Memories: an Application-centric Analysis

Author(s): Giulio Stramondo, Catalin Ciobanu, Ana Lucia Varbanescu
Published in: 2016

Abacus turn model-based routing for NoC interconnects with switch or link failures

Author(s): Poona Bahrebar, Dirk Stroobandt
Published in: Microprocessors and Microsystems, Issue 59, 2018, Page(s) 69-91, ISSN 0141-9331
DOI: 10.1016/j.micpro.2018.01.005

Quantum Chemistry in Dataflow: Density-Fitting MP2

Author(s): Bridgette Cooper, Stephen Girdlestone, Pavel Burovskiy, Georgi Gaydadjiev, Vitali Averbukh, Peter J. Knowles, Wayne Luk
Published in: Journal of Chemical Theory and Computation, Issue 13/11, 2017, Page(s) 5265-5272, ISSN 1549-9618
DOI: 10.1021/acs.jctc.7b00649

How Preserving Circuit Design Hierarchy During FPGA Packing Leads to Better Performance

Author(s): Dries Vercruyce, Elias Vansteenkiste, Dirk Stroobandt
Published in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Issue 37/3, 2018, Page(s) 629-642, ISSN 0278-0070
DOI: 10.1109/TCAD.2017.2717786

FP-BNN: Binarized neural network on FPGA

Author(s): Shuang Liang, Shouyi Yin, Leibo Liu, Wayne Luk, Shaojun Wei
Published in: Neurocomputing, Issue 275, 2018, Page(s) 1072-1086, ISSN 0925-2312
DOI: 10.1016/j.neucom.2017.09.046

Run-time Reconfigurable Acceleration for Genetic Programming Fitness Evaluation in Trading Strategies

Author(s): Andreea-Ingrid Funie, Paul Grigoras, Pavel Burovskiy, Wayne Luk, Mark Salmon
Published in: Journal of Signal Processing Systems, Issue 90/1, 2018, Page(s) 39-52, ISSN 1939-8018
DOI: 10.1007/s11265-017-1244-8

How to Efficiently Reconfigure Tunable Lookup Tables for Dynamic Circuit Specialization

Author(s): Amit Kulkarni, Dirk Stroobandt
Published in: International Journal of Reconfigurable Computing, Issue 2016, 2016, Page(s) 1-12, ISSN 1687-7195
DOI: 10.1155/2016/5340318

Floorplanning Automation for Partial-Reconfigurable FPGAs via Feasible Placements Generation

Author(s): Marco Rabozzi, Gianluca Carlo Durelli, Antonio Miele, John Lillis, Marco Domenico Santambrogio
Published in: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Issue 25/1, 2017, Page(s) 151-164, ISSN 1063-8210
DOI: 10.1109/TVLSI.2016.2562361

MiCAP-Pro: a high speed custom reconfiguration controller for Dynamic Circuit Specialization

Author(s): Amit Kulkarni, Dirk Stroobandt
Published in: Design Automation for Embedded Systems, Issue 20/4, 2016, Page(s) 341-359, ISSN 0929-5585
DOI: 10.1007/s10617-016-9180-6

On How to Accelerate Iterative Stencil Loops

Author(s): Riccardo Cattaneo, Giuseppe Natale, Carlo Sicignano, Donatella Sciuto, Marco Domenico Santambrogio
Published in: ACM Transactions on Architecture and Code Optimization, Issue 12/4, 2016, Page(s) 1-26, ISSN 1544-3566
DOI: 10.1145/2842615

Performance-driven instrumentation and mapping strategies using the LARA aspect-oriented programming approach

Author(s): João M. P. Cardoso, José G. F. Coutinho, Tiago Carvalho, Pedro C. Diniz, Zlatko Petrov, Wayne Luk, Fernando Gonçalves
Published in: Software: Practice and Experience, Issue 46/2, 2016, Page(s) 251-287, ISSN 0038-0644
DOI: 10.1002/spe.2301

Leveraging FPGAs for Accelerating Short Read Alignment

Author(s): James Arram, Thomas Kaplan, Wayne Luk, Peiyong Jiang
Published in: IEEE/ACM Transactions on Computational Biology and Bioinformatics, 2017, Page(s) 1-1, ISSN 1545-5963
DOI: 10.1109/TCBB.2016.2535385

A Domain Specific Approach to High Performance Heterogeneous Computing

Author(s): Gordon Inggs, David B. Thomas, Wayne Luk
Published in: IEEE Transactions on Parallel and Distributed Systems, Issue 28/1, 2017, Page(s) 2-15, ISSN 1045-9219
DOI: 10.1109/TPDS.2016.2563427

NeuroFlow: A General Purpose Spiking Neural Network Simulation Platform using Customizable Processors

Author(s): Kit Cheung, Simon R. Schultz, Wayne Luk
Published in: Frontiers in Neuroscience, Issue 9, 2016, ISSN 1662-453X
DOI: 10.3389/fnins.2015.00516

Transparent In-Circuit Assertions for FPGAs

Author(s): Eddie Hung, Tim Todman, Wayne Luk
Published in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2017, Page(s) 1-1, ISSN 0278-0070
DOI: 10.1109/TCAD.2016.2618862

Chapter Four - Data Flow Computing in Geoscience Applications

Author(s): L. Gan, H. Fu, O. Mencer, W. Luk, G. Yang
Published in: 2017, Page(s) 125-158
DOI: 10.1016/bs.adcom.2016.09.005