Exploiting eXascale Technology with Reconfigurable Architectures

Resultado final

Project Handbook, e-mail reflector, web site and FTP site

Writing of the project Handbook setting up an email reflector web site and FTP site

Initial demonstrators

Result of T2.3

Integration and final demonstrators

This is the result of T2.4

Publicaciones

Optimizing streaming stencil time-step designs via FPGA floorplanning

Autores: Marco Rabozzi, Giuseppe Natale, Biagio Festa, Antonio Miele, Marco D. Santambrogio
Publicado en: 2017 27th International Conference on Field Programmable Logic and Applications (FPL), 2017, Página(s) 1-4, ISBN 978-9-0903-0428-1
Editor: IEEE
DOI: 10.23919/FPL.2017.8056764

FPGA-based PairHMM Forward Algorithm for DNA Variant Calling

Autores: Davide Sampietro, Chiara Crippa, Lorenzo Di Tucci, Emanuele Del Sozzo, Marco D. Santambrogio
Publicado en: 2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2018, Página(s) 1-8, ISBN 978-1-5386-7479-6
Editor: IEEE
DOI: 10.1109/ASAP.2018.8445119

Heterogeneous exascale supercomputing: The role of CAD in the exaFPGA project

Autores: M. Rabozzi, G. Natale, E. Del Sozzo, A. Scolari, L. Stornaiuolo, M. D. Santambrogio
Publicado en: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, 2017, Página(s) 410-415, ISBN 978-3-9815370-8-6
Editor: IEEE
DOI: 10.23919/DATE.2017.7927025

CGRA Tool Flow for Fast Run-Time Reconfiguration

Autores: Florian Fricke, André Werner, Keyvan Shahin, Michael Huebner
Publicado en: Proc. of the 14th International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), 2018, Página(s) 661-672
Editor: Springer International Publishing
DOI: 10.1007/978-3-319-78890-6_53

Superimposed in-circuit debugging for self-healing FPGA overlays

Autores: Alexandra Kourfali, Dirk Stroobandt
Publicado en: 2018 IEEE 19th Latin-American Test Symposium (LATS), 2018, Página(s) 1-6, ISBN 978-1-5386-1472-3
Editor: IEEE
DOI: 10.1109/LATW.2018.8349688

Tool flow for automatic generation of architectures and test-cases to enable the evaluation of CGRAs in the context of HPC applications

Autores: Florian Fricke, Andre Werner, Michael Hubner
Publicado en: 2017 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2017, Página(s) 1-2, ISBN 978-1-5386-3534-6
Editor: IEEE
DOI: 10.1109/DASIP.2017.8122124

Hardware Compilation of Deep Neural Networks: An Overview

Autores: Ruizhe Zhao, Shuanglong Liu, Ho-Cheung Ng, Erwei Wang, James J. Davis, Xinyu Niu, Xiwei Wang, Huifeng Shi, George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
Publicado en: 2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2018, Página(s) 1-8, ISBN 978-1-5386-7479-6
Editor: IEEE
DOI: 10.1109/ASAP.2018.8445088

SICTA: A superimposed in-circuit fault tolerant architecture for SRAM-based FPGAs

Autores: Alexandra Kourfali, Amit Kulkarni, Dirk Stroobandt
Publicado en: 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS), 2017, Página(s) 5-8, ISBN 978-1-5386-0352-9
Editor: IEEE
DOI: 10.1109/IOLTS.2017.8046168

ADAM - Automated Design Analysis and Merging for Speeding up FPGA Development

Autores: Ho-Cheung Ng, Shuanglong Liu, Wayne Luk
Publicado en: Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays - FPGA '18, 2018, Página(s) 189-198, ISBN 9781-450356145
Editor: ACM Press
DOI: 10.1145/3174243.3174247

Hierarchical force-based block spreading for analytical FPGA placement

Autores: Dries Vercruyce, Elias Vansteenkiste, Dirk Stroobandt
Publicado en: FPL 2018, 2018
Editor: IEEE

The Role of CAD Frameworks in Heterogeneous FPGA-Based Cloud Systems

Autores: Lorenzo Di Tucci, Marco Rabozzi, Luca Stornaiuolo, Marco D. Santambrogio
Publicado en: 2017 IEEE International Conference on Computer Design (ICCD), 2017, Página(s) 423-426, ISBN 978-1-5386-2254-4
Editor: IEEE
DOI: 10.1109/ICCD.2017.74

CRRS: Custom Regression and Regularisation Solver for Large-scale Linear Systems,

Autores: A.-I. Cross, L. Guo, W. Luk and M. Salmon
Publicado en: International Conference on Field-Programmable Logic and Applications, 2018
Editor: IEEE

A NoC-based custom FPGA configuration memory architecture for ultra-fast micro-reconfiguration

Autores: Amit Kulkarni, Poona Bahrebar, Dirk Stroobandt, Giulio Stramondo, Catalin Bogdan Ciobanu, Ana Lucia Varbanescu
Publicado en: 2017 International Conference on Field Programmable Technology (ICFPT), 2017, Página(s) 203-206, ISBN 978-1-5386-2656-6
Editor: IEEE
DOI: 10.1109/FPT.2017.8280141

An open reconfigurable research platform as stepping stone to exascale high-performance computing

Autores: Dirk Stroobandt, Catalin Bogdan Ciobanu, Marco D. Santambrogio, Gabriel Figueiredo, Andreas Brokalakis, Dionisios Pnevmatikatos, Michael Huebner, Tobias Becker, Alex J. W. Thom
Publicado en: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, 2017, Página(s) 416-421, ISBN 978-3-9815370-8-6
Editor: IEEE
DOI: 10.23919/DATE.2017.7927026

Towards Application-Centric Parallel Memories

Autores: Giulio Stramondo, Catalin Bogdan Ciobanu, Ana Lucia Varbanescu and Cees De Laat
Publicado en: EuroPar Workshops 2018 -- HeteroPar'18, 2018
Editor: IEEE

From Tensor Algebra to Hardware Accelerators: Generating Streaming Architectures for Solving Partial Differential Equations

Autores: Francis P. Russell, James Stanley Targett, Wayne Luk
Publicado en: 2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2018, Página(s) 1-8, ISBN 978-1-5386-7479-6
Editor: IEEE
DOI: 10.1109/ASAP.2018.8445093

A Parallel, Energy Efficient Hardware Architecture for the merAligner on FPGA Using Chisel HCL

Autores: Lorenzo Di Tucci, Davide Conficconi, Alessandro Comodi, Steven Hofmeyr, David Donofrio, Marco D. Santambrogio
Publicado en: 2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2018, Página(s) 214-217, ISBN 978-1-5386-5555-9
Editor: IEEE
DOI: 10.1109/IPDPSW.2018.00041

In-Circuit FPGA Debugging using Parameterised Reconfigurations

Autores: Alexandra Kourfali and Dirk Stroobandt
Publicado en: 54th ACM/ESDA/IEEE Design Automation Conference (DAC), 2017
Editor: IEEE

Superimposed In-Circuit Fault Mitigation for Dynamically Reconfigurable FPGAs

Autores: Alexandra Kourfali, David Merodio Codinachs and Dirk Stroobandt
Publicado en: IEEE Conference on Radiation Effects on Components and Systems (RADECS), 2017
Editor: IEEE

An FPGA-Based Acceleration Methodology and Performance Model for Iterative Stencils

Autores: Enrico Reggiani, Giuseppe Natale, Carlo Moroni, Marco D. Santambrogio
Publicado en: 2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2018, Página(s) 115-122, ISBN 978-1-5386-5555-9
Editor: IEEE
DOI: 10.1109/IPDPSW.2018.00026

Towards Hardware Accelerated Reinforcement Learning for Application-Specific Robotic Control

Autores: Shengjia Shao, Jason Tsai, Michal Mysior, Wayne Luk, Thomas Chau, Alexander Warren, Ben Jeppesen
Publicado en: 2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2018, Página(s) 1-8, ISBN 978-1-5386-7479-6
Editor: IEEE
DOI: 10.1109/ASAP.2018.8445099

From exaflop to exaflow

Autores: Tobias Becker, Pavel Burovskiy, Anna Maria Nestorov, Hristina Palikareva, Enrico Reggiani, Georgi Gaydadjiev
Publicado en: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, 2017, Página(s) 404-409, ISBN 978-3-9815370-8-6
Editor: IEEE
DOI: 10.23919/DATE.2017.7927024

MAX-PolyMem: High-Bandwidth Polymorphic Parallel Memories for DFEs

Autores: Catalin Bogdan Ciobanu, Giulio Stramondo, Cees de Laat, Ana Lucia Varbanescu
Publicado en: 2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2018, Página(s) 107-114, ISBN 978-1-5386-5555-9
Editor: IEEE
DOI: 10.1109/IPDPSW.2018.00025

Towards Efficient Convolutional Neural Network for Domain-Specific Applications on FPGA

Autores: R. Zhao, H.C. Ng, W. Luk and X. Niu
Publicado en: International Conference on Field-Programmable Logic and Applications, 2018
Editor: IEEE

HLS Support for Polymorphic Parallel Memories

Autores: Luca Stornaiuolo, Marco Rabozzi, Marco D. Santambrogio, Donatella Sciuto, Giulio Stramondo, Catalin Bogdan Ciobanu, Ana Lucia Varbanescu
Publicado en: proceeding of the 26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2018
Editor: IEEE

OXiGen: A Tool for Automatic Acceleration of C Functions Into Dataflow FPGA-Based Kernels

Autores: Francesco Peverelli, Marco Rabozzi, Emanuele Del Sozzo, Marco D. Santambrogio
Publicado en: 2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2018, Página(s) 91-98, ISBN 978-1-5386-5555-9
Editor: IEEE
DOI: 10.1109/IPDPSW.2018.00023

Accelerated Inference of Positive Selection on Whole Genomes

Autores: Nikolaos Alachiotis, Charalampos Vatsolakis, Grigorios Chrysos and Dionisios N. Pnevmatikatos
Publicado en: International Conference on Field-Programmable Logic and Applications, 2018
Editor: IEEE

A CAD Open Platform for High Performance Reconfigurable Systems in the EXTRA Project

Autores: Marco Rabozzi, Rolando Brondolin, Giuseppe Natale, Emanuele Del Sozzo, Michael Huebner, Andreas Brokalakis, Catalin Ciobanu, Dirk Stroobandt, Marco Domenico Santambrogio
Publicado en: 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2017, Página(s) 368-373, ISBN 978-1-5090-6762-6
Editor: IEEE
DOI: 10.1109/ISVLSI.2017.71

Liquid: High quality scalable placement for large heterogeneous FPGAs

Autores: Dries Vercruyce, Elias Vansteenkiste, Dirk Stroobandt
Publicado en: 2017 International Conference on Field Programmable Technology (ICFPT), 2017, Página(s) 17-24, ISBN 978-1-5386-2656-6
Editor: IEEE
DOI: 10.1109/FPT.2017.8280116

A Scalable FPGA Design for Cloud N-Body Simulation

Autores: Emanuele Del Sozzo, Marco Rabozzi, Lorenzo Di Tucci, Donatella Sciuto, Marco D. Santambrogio
Publicado en: 2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2018, Página(s) 1-8, ISBN 978-1-5386-7479-6
Editor: IEEE
DOI: 10.1109/ASAP.2018.8445106

EXTRA: An Open Platform for Reconfigurable Architectures

Autores: Catalin Bogdan Ciobanu, Giulio Stramondo, Ana Lucia Varbanescu, Andreas Brokalakis, Antonis Nikitakis, Lorenzo Di Tucci, Marco Rabozzi, Luca Stornaiuolo, Marco D. Santambrogio, Grigorios Chrysos, Charalampos Vatsolakis, Charitopoulos Georgios, Dionisios Pnevmatikatos
Publicado en: Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XVIII), 2018 International Conference on, 2018
Editor: IEEE
DOI: 10.1145/3229631.3236092

A generic high throughput architecture for stream processing

Autores: Christes Rousopoulos, Ektoras Karandeinos, Grigorios Chrysos, Apostolos Dollas, Dionisios N. Pnevmatikatos
Publicado en: 2017 27th International Conference on Field Programmable Logic and Applications (FPL), 2017, Página(s) 1-5, ISBN 978-9-0903-0428-1
Editor: IEEE
DOI: 10.23919/FPL.2017.8056796

Five-point algorithm: An efficient cloud-based FPGA implementation

Autores: Marco Rabozzi, Emanuele Del Sozzo, Lorenzo Di Tucci, Marco D. Santambrogio
Publicado en: 2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2018, Página(s) 1-8, ISBN 978-1-5386-7479-6
Editor: IEEE
DOI: 10.1109/ASAP.2018.8445097

A decoupled access-execute architecture for reconfigurable accelerators

Autores: George Charitopoulos, Charalampos Vatsolakis, Grigorios Chrysos, Dionisios N. Pnevmatikatos
Publicado en: Proceedings of the 15th ACM International Conference on Computing Frontiers - CF '18, 2018, Página(s) 244-247, ISBN 9781-450357616
Editor: ACM Press
DOI: 10.1145/3203217.3203267

Online reconfigurable routing method for handling link failures in NoC-based MPSoCs

Autores: Poona Bahrebar, Dirk Stroobandt
Publicado en: 2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2016, Página(s) 1-8, ISBN 978-1-5090-2520-6
Editor: IEEE
DOI: 10.1109/ReCoSoC.2016.7533905

Runtime-quality tradeoff in partitioning based multithreaded packing

Autores: Dries Vercruyce, Elias Vansteenkiste, Dirk Stroobandt
Publicado en: 2016 26th International Conference on Field Programmable Logic and Applications (FPL), 2016, Página(s) 1-9, ISBN 978-2-8399-1844-2
Editor: IEEE
DOI: 10.1109/FPL.2016.7577300

Efficient Hardware Debugging Using Parameterized FPGA Reconfiguration

Autores: Alexandra Kourfali, Dirk Stroobandt
Publicado en: 2016 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2016, Página(s) 277-282, ISBN 978-1-5090-3682-0
Editor: IEEE
DOI: 10.1109/IPDPSW.2016.95

A 16-Bit Reconfigurable Encryption Processor for p-Cipher

Autores: Mohamed El-Hadedy, Hristina Mihajloska, Danilo Gligoroski, Amit Kulkarni, Dirk Stroobandt, Kevin Skadron
Publicado en: 2016 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2016, Página(s) 162-171, ISBN 978-1-5090-3682-0
Editor: IEEE
DOI: 10.1109/IPDPSW.2016.27

MiCAP: a custom reconfiguration controller for dynamic circuit specialization

Autores: Amit Kulkarni, Vipin Kizheppatt, Dirk Stroobandt
Publicado en: 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2015, Página(s) 1-6, ISBN 978-1-4673-9406-2
Editor: IEEE
DOI: 10.1109/ReConFig.2015.7393327

Hardware Design Automation of Convolutional Neural Networks

Autores: Andrea Solazzo, Emanuele Del Sozzo, Irene De Rose, Matteo De Silvestri, Gianluca C. Durelli, Marco D. Santambrogio
Publicado en: 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2016, Página(s) 224-229, ISBN 978-1-4673-9039-2
Editor: IEEE
DOI: 10.1109/ISVLSI.2016.101

Pixie: A heterogeneous Virtual Coarse-Grained Reconfigurable Array for high performance image processing applications

Autores: A. Kulkarni, A. Werner, F. Fricke, D. Stroobandt and M. Huebner
Publicado en: 3rd International Workshop on Overlay Architectures for FPGAs (OLAF2017), 2017
Editor: IEEE

EXTRA: Towards the exploitation of eXascale technology for reconfigurable architectures

Autores: Dirk Stroobandt, Ana Lucia Varbanescu, Catalin Bogdan Ciobanu, Muhammed Al Kadi, Andreas Brokalakis, George Charitopoulos, Tim Todman, Xinyu Niu, Dionisios Pnevmatikatos, Amit Kulkarni, Elias Vansteenkiste, Wayne Luk, Marco D. Santambrogio, Donatella Sciuto, Michael Huebner, Tobias Becker, Georgi Gaydadjiev, Antonis Nikitakis, Alex J. W. Thom
Publicado en: 2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2016, Página(s) 1-7, ISBN 978-1-5090-2520-6
Editor: IEEE
DOI: 10.1109/ReCoSoC.2016.7533896

An FPGA-based high-throughput stream join architecture

Autores: Charalabos Kritikakis, Grigorios Chrysos, Apostolos Dollas, Dionisios N. Pnevmatikatos
Publicado en: 2016 26th International Conference on Field Programmable Logic and Applications (FPL), 2016, Página(s) 1-4, ISBN 978-2-8399-1844-2
Editor: IEEE
DOI: 10.1109/FPL.2016.7577354

Design and exploration of routing methods for NoC-based multicore systems

Autores: Poona Bahrebar, Dirk Stroobandt
Publicado en: 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2015, Página(s) 1-4, ISBN 978-1-4673-9406-2
Editor: IEEE
DOI: 10.1109/ReConFig.2015.7393296

EXTRA: Towards an Efficient Open Platform for Reconfigurable High Performance Computing

Autores: Catalin Bogdan Ciobanu, Ana Lucia Varbanescu, Dionisios Pnevmatikatos, George Charitopoulos, Xinyu Niu, Wayne Luk, Marco D. Santambrogio, Donatella Sciuto, Muhammed Al Kadi, Michael Huebner, Tobias Becker, Georgi Gaydadjiev, Andreas Brokalakis, Antonis Nikitakis, Alex J. W. Thom, Elias Vansteenkiste, Dirk Stroobandt
Publicado en: 2015 IEEE 18th International Conference on Computational Science and Engineering, 2015, Página(s) 339-342, ISBN 978-1-4673-8297-7
Editor: IEEE
DOI: 10.1109/CSE.2015.54

A Fully Parameterized Virtual Coarse Grained Reconfigurable Array for High Performance Computing Applications

Autores: Amit Kulkarni, Elias Vasteenkiste, Dirk Stroobandt, Andreas Brokalakis, Antonios Nikitakis
Publicado en: 2016 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2016, Página(s) 265-270, ISBN 978-1-5090-3682-0
Editor: IEEE
DOI: 10.1109/IPDPSW.2016.13

A polyhedral model-based framework for dataflow implementation on FPGA devices of iterative stencil loops

Autores: Giuseppe Natale, Giulio Stramondo, Pietro Bressana, Riccardo Cattaneo, Donatella Sciuto, Marco D. Santambrogio
Publicado en: Proceedings of the 35th International Conference on Computer-Aided Design - ICCAD '16, 2016, Página(s) 1-8, ISBN 9781-450344661
Editor: ACM Press
DOI: 10.1145/2966986.2966995

Heterogeneous exascale supercomputing: the role of CAD in the exaFPGA project

Autores: M. Rabozzi, G. Natale, E. Del Sozzo, A. Scolari, L. Stornaiuolo, and M. D. Santambrogio
Publicado en: 2017 Design, Automation Test in Europe Conference Exhibition (DATE), 2017
Editor: ACM

On the Automation of High Level Synthesis of Convolutional Neural Networks

Autores: Emanuele Del Sozzo, Andrea Solazzo, Antonio Miele, Marco D. Santambrogio
Publicado en: 2016 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2016, Página(s) 217-224, ISBN 978-1-5090-3682-0
Editor: IEEE
DOI: 10.1109/IPDPSW.2016.153

Towards a Performance-Aware Power Capping Orchestrator for the Xen Hypervisor

Autores: M. Arnaboldi, M. Ferroni, M. D. Santambrogio
Publicado en: Embed With Linux (EWiLi) Workshop 2016, 2016
Editor: NN

ProFAX: A hardware acceleration of a protein folding algorithm

Autores: Giulia Guidi, Lorenzo Di Tucci, Marco D. Santambrogio
Publicado en: 2016 IEEE 2nd International Forum on Research and Technologies for Society and Industry Leveraging a better tomorrow (RTSI), 2016, Página(s) 1-6, ISBN 978-1-5090-1131-5
Editor: IEEE
DOI: 10.1109/RTSI.2016.7740584

Knowledge Transfer in Automatic Optimisation of Reconfigurable Designs

Autores: Maciej Kurek, Marc Peter Deisenroth, Wayne Luk, Timothy Todman
Publicado en: 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2016, Página(s) 84-87, ISBN 978-1-5090-2356-1
Editor: IEEE
DOI: 10.1109/FCCM.2016.29

EURECA compilation: Automatic optimisation of cycle-reconfigurable circuits

Autores: Xinyu Niu, Nicholas Ng, Tomofumi Yuki, Shaojun Wang, Nobuko Yoshida, Wayne Luk
Publicado en: 2016 26th International Conference on Field Programmable Logic and Applications (FPL), 2016, Página(s) 1-4, ISBN 978-2-8399-1844-2
Editor: IEEE
DOI: 10.1109/FPL.2016.7577359

F-CNN: An FPGA-based framework for training Convolutional Neural Networks

Autores: Wenlai Zhao, Haohuan Fu, Wayne Luk, Teng Yu, Shaojun Wang, Bo Feng, Yuchun Ma, Guangwen Yang
Publicado en: 2016 IEEE 27th International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2016, Página(s) 107-114, ISBN 978-1-5090-1503-0
Editor: IEEE
DOI: 10.1109/ASAP.2016.7760779

A Domain Specific Language for accelerated Multilevel Monte Carlo simulations

Autores: Ben Lindsey, Matthew Leslie, Wayne Luk
Publicado en: 2016 IEEE 27th International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2016, Página(s) 99-106, ISBN 978-1-5090-1503-0
Editor: IEEE
DOI: 10.1109/ASAP.2016.7760778

A Scalable Dataflow Accelerator for Real Time Onboard Hyperspectral Image Classification

Autores: Shaojun Wang, Xinyu Niu, Ning Ma, Wayne Luk, Philip Leong, Yu Peng
Publicado en: Part of the Lecture Notes in Computer Science book series (LNCS, volume 9625), 2016, Página(s) 105-116
Editor: Springer International Publishing
DOI: 10.1007/978-3-319-30481-6_9

Connect on the fly: Enhancing and prototyping of cycle-reconfigurable modules

Autores: Hao Zhou, Xinyu Niu, Junqi Yuan, Lingli Wang, Wayne Luk
Publicado en: 2016 26th International Conference on Field Programmable Logic and Applications (FPL), 2016, Página(s) 1-8, ISBN 978-2-8399-1844-2
Editor: IEEE
DOI: 10.1109/FPL.2016.7577332

Optimising Sparse Matrix Vector multiplication for large scale FEM problems on FPGA

Autores: Paul Grigoras, Pavel Burovskiy, Wayne Luk, Spencer Sherwin
Publicado en: 2016 26th International Conference on Field Programmable Logic and Applications (FPL), 2016, Página(s) 1-9, ISBN 978-2-8399-1844-2
Editor: IEEE
DOI: 10.1109/FPL.2016.7577352

CASK - Open-Source Custom Architectures for Sparse Kernels

Autores: Paul Grigoras, Pavel Burovskiy, Wayne Luk
Publicado en: Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays - FPGA '16, 2016, Página(s) 179-184, ISBN 9781-450338561
Editor: ACM Press
DOI: 10.1145/2847263.2847338

A Decoupled Access-Execute Architecture for Reconfigurable Accelerators

Autores: George Charitopoulos, Charalampos Vatsolakis, Stefanos Sidiropoulos, Grigorios Chrysos and Dionisios Pnevmatikatos
Publicado en: 11th HiPEAC Workshop on Reconfigurable Computing (WRC'2017), 2017
Editor: NN

Customizable Memory Systems for High Performance Reconfigurable Architectures

Autores: Catalin Ciobanu, Giulio Stramondo, Ana Lucia Varbanescu
Publicado en: International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded (ACACES) 2016, 2016
Editor: NN

A Scalable Dataflow Implementation of Curran’s Approximation Algorithm

Autores: Anna Maria Nestorov, Enrico Reggiani, Marco Domenico Santambrogio, Pavel Burovskiy, Hristina Palikareva and Tobias Becker
Publicado en: Reconfigurable Architectures Workshop, 2017
Editor: NN

From exaflop to exaflow

Autores: • Tobias Becker, Pavel Burovskiy, Anna Maria Nestorov, Hristina Palikareva, Enrico Reggiani, Georgi Gaydadjiev
Publicado en: Proceedings of the Design Automation and Test in Europe Conference, 2017
Editor: NN

How effective are custom parallel memories

Autores: Giulio Stramondo, Ana Lucia Varbanescu and Catalin Bogdan Ciobanu
Publicado en: ICT.Open, 2017
Editor: NN

The Case for Custom Parallel Memories: an Application-centric Analysis

Autores: Giulio Stramondo, Catalin Ciobanu, Ana Lucia Varbanescu
Publicado en: 2016
Editor: NN

Abacus turn model-based routing for NoC interconnects with switch or link failures

Autores: Poona Bahrebar, Dirk Stroobandt
Publicado en: Microprocessors and Microsystems, Edición 59, 2018, Página(s) 69-91, ISSN 0141-9331
Editor: Elsevier BV
DOI: 10.1016/j.micpro.2018.01.005

Quantum Chemistry in Dataflow: Density-Fitting MP2

Autores: Bridgette Cooper, Stephen Girdlestone, Pavel Burovskiy, Georgi Gaydadjiev, Vitali Averbukh, Peter J. Knowles, Wayne Luk
Publicado en: Journal of Chemical Theory and Computation, Edición 13/11, 2017, Página(s) 5265-5272, ISSN 1549-9618
Editor: American Chemical Society
DOI: 10.1021/acs.jctc.7b00649

How Preserving Circuit Design Hierarchy During FPGA Packing Leads to Better Performance

Autores: Dries Vercruyce, Elias Vansteenkiste, Dirk Stroobandt
Publicado en: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Edición 37/3, 2018, Página(s) 629-642, ISSN 0278-0070
Editor: Institute of Electrical and Electronics Engineers
DOI: 10.1109/TCAD.2017.2717786

FP-BNN: Binarized neural network on FPGA

Autores: Shuang Liang, Shouyi Yin, Leibo Liu, Wayne Luk, Shaojun Wei
Publicado en: Neurocomputing, Edición 275, 2018, Página(s) 1072-1086, ISSN 0925-2312
Editor: Elsevier BV
DOI: 10.1016/j.neucom.2017.09.046

Run-time Reconfigurable Acceleration for Genetic Programming Fitness Evaluation in Trading Strategies

Autores: Andreea-Ingrid Funie, Paul Grigoras, Pavel Burovskiy, Wayne Luk, Mark Salmon
Publicado en: Journal of Signal Processing Systems, Edición 90/1, 2018, Página(s) 39-52, ISSN 1939-8018
Editor: Springer Verlag
DOI: 10.1007/s11265-017-1244-8

How to Efficiently Reconfigure Tunable Lookup Tables for Dynamic Circuit Specialization

Autores: Amit Kulkarni, Dirk Stroobandt
Publicado en: International Journal of Reconfigurable Computing, Edición 2016, 2016, Página(s) 1-12, ISSN 1687-7195
Editor: Hindawi Publishing Corporation
DOI: 10.1155/2016/5340318

Floorplanning Automation for Partial-Reconfigurable FPGAs via Feasible Placements Generation

Autores: Marco Rabozzi, Gianluca Carlo Durelli, Antonio Miele, John Lillis, Marco Domenico Santambrogio
Publicado en: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Edición 25/1, 2017, Página(s) 151-164, ISSN 1063-8210
Editor: Institute of Electrical and Electronics Engineers
DOI: 10.1109/TVLSI.2016.2562361

MiCAP-Pro: a high speed custom reconfiguration controller for Dynamic Circuit Specialization

Autores: Amit Kulkarni, Dirk Stroobandt
Publicado en: Design Automation for Embedded Systems, Edición 20/4, 2016, Página(s) 341-359, ISSN 0929-5585
Editor: Kluwer Academic Publishers
DOI: 10.1007/s10617-016-9180-6

On How to Accelerate Iterative Stencil Loops

Autores: Riccardo Cattaneo, Giuseppe Natale, Carlo Sicignano, Donatella Sciuto, Marco Domenico Santambrogio
Publicado en: ACM Transactions on Architecture and Code Optimization, Edición 12/4, 2016, Página(s) 1-26, ISSN 1544-3566
Editor: Association for Computing Machinary, Inc.
DOI: 10.1145/2842615

Performance-driven instrumentation and mapping strategies using the LARA aspect-oriented programming approach

Autores: João M. P. Cardoso, José G. F. Coutinho, Tiago Carvalho, Pedro C. Diniz, Zlatko Petrov, Wayne Luk, Fernando Gonçalves
Publicado en: Software: Practice and Experience, Edición 46/2, 2016, Página(s) 251-287, ISSN 0038-0644
Editor: John Wiley & Sons Inc.
DOI: 10.1002/spe.2301

Leveraging FPGAs for Accelerating Short Read Alignment

Autores: James Arram, Thomas Kaplan, Wayne Luk, Peiyong Jiang
Publicado en: IEEE/ACM Transactions on Computational Biology and Bioinformatics, 2017, Página(s) 1-1, ISSN 1545-5963
Editor: IEEE Computer Society
DOI: 10.1109/TCBB.2016.2535385

A Domain Specific Approach to High Performance Heterogeneous Computing

Autores: Gordon Inggs, David B. Thomas, Wayne Luk
Publicado en: IEEE Transactions on Parallel and Distributed Systems, Edición 28/1, 2017, Página(s) 2-15, ISSN 1045-9219
Editor: Institute of Electrical and Electronics Engineers
DOI: 10.1109/TPDS.2016.2563427

NeuroFlow: A General Purpose Spiking Neural Network Simulation Platform using Customizable Processors

Autores: Kit Cheung, Simon R. Schultz, Wayne Luk
Publicado en: Frontiers in Neuroscience, Edición 9, 2016, ISSN 1662-453X
Editor: NN
DOI: 10.3389/fnins.2015.00516

Transparent In-Circuit Assertions for FPGAs

Autores: Eddie Hung, Tim Todman, Wayne Luk
Publicado en: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2017, Página(s) 1-1, ISSN 0278-0070
Editor: Institute of Electrical and Electronics Engineers
DOI: 10.1109/TCAD.2016.2618862

Chapter Four - Data Flow Computing in Geoscience Applications

Autores: L. Gan, H. Fu, O. Mencer, W. Luk, G. Yang
Publicado en: 2017, Página(s) 125-158
Editor: Elsevier
DOI: 10.1016/bs.adcom.2016.09.005

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