This project aims to make significant advances in logic synthesis by exploiting new models such as binary decision diagrams, and to establish a better link with practical issues such as wiring problems and connection to layout generators. It also aims to create a better link with architectural synthesis. For this purpose the logic synthesis methods proposed have to be very robust with respect to complexity and to be able to handle more efficiently the existence of generators and library blocks. Moreover, any restricted technology target, such as a standard cell, is avoided, and new devices, especially CPLDs and FPGAs, widely addressed.
The research addresses logic synthesis, focusing on new models as well as a better understanding of the connection to various technological targets, controller synthesis coping with high complexity and using block generators, and architectural design including the use of library blocks and parameterized generators.
For logic synthesis the state of the art is changing very rapidly due to the extensive use of new representations for Boolean functions, namely the binary decision diagrams. This provides an opening for new synthesis tools which may provide a significant gain both in results (area and performance) and in running time and memory space. Significant progress has been made in binary decision diagrams construction, input order selection and in the different use of these representations for synthesis on various targets. Specific mappers on field programmable gate array (FPGA and CPLD) targets led to immediate technology transfers and improvements on standard cells synthesis were identified. For FPGA and CPLD, innovative microgenerators are provided and efficient partitioning is effected. For controller synthesis, a unique dedicated synthesis tool for ultralarge Moore controllers described in verifiable hardware description language (VHDL) and using read only memory (ROM) generators is available. Extension to the use of communicating finite state machines or hierarchical finite state machines is in progress.
Architectural synthesis, focuses on the impact of parameterized generators, on data path synthesizers and on automatic synthesis tools from VHDL.
APPROACH AND METHODS
The proposed methods concern three areas:
- Logic synthesis: new models (binary decision diagrams, lexicographical expressions) are investigated and should bring double benefit. They cope better with complexity and take into account wiring and critical path minimisation. Synthesis on FGPAs CPLDs and Standard cells is addresed.
- Controller synthesis: new proposed synthesis methods handle highly complex controllers more efficiently than traditional FSM synthesis tools. They synthesise hierarchical or distributed controllers and use generators such as ROM generators.
- Architectural design: this task, mainly, focuses on a better link between RTL level or high level from VHDL to layout with a special emphasis on the use of parameterised blocks, generators and data path synthesisers.
This project aims to improve the theoretical state-of-the-art of logic synthesis and brings some new highlights to practical issues such as wiring and timing aspects. An important technology transfer effort towards industry is being undertaken by several partners and successful products have emerged. Companies directly involved in the project will benefit from the results, and most academic members are directly engaged in transfers towards industry (IMEC, INPG, Karlsruhe). As an example a start up marketing the results of this projects sells up to 2000 licenses of a synthesis tool in 1992/93.
5600 MB Eindhoven