Validation of European high capacity rad-hard FPGA and software tools

Project Information

VEGAS

Grant agreement ID: 687220

DOI

10.3030/687220

Project closed

EC signature date 23 November 2015

Start date 1 January 2016

End date 31 August 2020

Funded under

• INDUSTRIAL LEADERSHIP - Leadership in enabling and industrial technologies – Space

Total cost

€ 3 976 861,25

EU contribution

€ 3 975 311,25

Coordinated by

NANOXPLORE
France

Periodic Reporting for period 3 - VEGAS (Validation of European high capacity rad-hard FPGA and software tools)

Reporting period: 2019-07-01 to 2020-08-31

Summary of the context and overall objectives of the project

Project VEGAS proposes to address this key challenge of European non-dependence and competitiveness regarding rad-hard FPGA for space applications. VEGAS will evaluate (following ESCC rules) and validate the first rad-hard FPGA in 65nm to directly compete with the US offering and reach TRL 7.
The proposed activity is part of a jointly agreed space FPGA roadmap between EU, the European Space Agency, the CNES and the key European space equipment manufacturers. It is supporting the Strategic Research Agenda of the European Space Technology Platform through various objectives such as:
• Preparing and enabling future European space programmes,
• Supporting the industry competitiveness (short term/time to market),
• Guaranteeing European technology independence,
• Fostering technology transfer
The proposed activities allow addressing applications beyond the space market such as avionic, energy and transport. These markets are close to the space market in terms of reliability and performance requirements and can be derived from the proposed development in a short time frame.
VEGAS offers a Key Enabling Technology to the European space industry. VEGAS will offer European space agencies and major customers the state-of-the-art components they need without having to worry about exportation regulations. Additional markets beyond aerospace will also be addressed. The main goal of VEGAS is indeed to validate and ESCC evaluate a rad-hard FPGA and associated CAD tools by integrating all the enabling design and manufacturing technologies needed to deliver high reliability, radiation-hardened integrated circuits. Our rad-hard FPGA will benefit from the most advanced space qualified technologies including 65nm ST librairy, flip chip assembly, large hermetic package etc.
The first ambition of VEGAS is to offer Europe new advanced rad-hard FPGA for space applications but also to serve additional markets sharing some harsh environment and high reliability requirements.

Work performed from the beginning of the project to the end of the period covered by the report and main results achieved so far

Project VEGAS has been completed: the NG-MEDIUM device has gone from a recently fabricated device to a fully space-qualified solution for space applications. The device also has gone from unknown to popular in both academic and industry circles, being a huge success in the space market.

Providing flight-ready technology: the VEGAS project has taken the NG-MEDIUM FPGA from a Technology Readiness Level (TRL) of 5 to a Technology Readiness Level of 7, which indicates it is ready to fly in space missions.

Reaching the market, shaping space: there is a massive business opportunity in the space sector, but this industry is traditionally conservative, due to the high risk of the projects involved, which entails a huge entry barrier for any new actors. The NG-MEDIUM FPGA is no longer a newcomer to this sector, having been chosen for a number of space projects, including at least one satellite constellation.

Reaching the industry and academic communities: a specific workshop, the BRAVE FPGA days, has been born during the VEGAS project, with great success in terms of attendees, sparking the interest of many actors in the space sector.

Improving the software tools to reach maximum chip potential: FPGA software tools are a critical part of the mix: they both shape the user experience and define whether the true potential of the device can be achieved. The software tools have been greatly improved in all aspects, such as resource usage inside the FPGA and maximum place and route frequency, with the input from the rest of the partners.

Reducing non-European dependency: at the end of the VEGAS project, Europe has now a fully-european FPGA, available without any import restrictions, that can be used for space missions and other harsh environments.

Enabling the future of European Space sector: this device, with the rest of the products of the family, such as the NG-Large and the NG-Ultra FPGAs, will enable the future of european space applications, reducing the dependence on critical technologies and capabilities from outside Europe.

Progress beyond the state of the art and expected potential impact (including the socio-economic impact and the wider societal implications of the project so far)

The two FPGA used in VEGAS will go beyond current state of the art and will be very competitive. The NG-FPGA-MEDIUM will directly compete with the RTAX 2000 and RTAX 4000 with a clear advantage of being fully reprogrammable and having advanced features such as dynamic partial reconfiguration or automatic internal scrubbing. The NG-FPGA-LARGE will compete with the Virtex 5QV from Xilinx and the upcoming RTG4 from Microsemi. The NG-FPGA-LARGE will have a better resilience to SEU than the Virtex 5QV and more additional features than the RTG4 such as Dynamic Partial Reconfiguration.

VEGAS will have the following impacts:
• Reduce the dependence on critical technologies and capabilities from outside Europe for future space applications by providing an ITAR free advanced rad-hard FPGA
• Develop or regain in the mid-term the European capacity to operate independently in space with access to new generation of rad-hard FPGA beyond current state of the art
• Enhance the technical capabilities and overall competitiveness of European space industry satellite vendors on the worldwide market by giving prime access to exportation restriction free high performance technologies
• Work package dedicated to the development of a commercial evaluation of the technology with a full range of recurring products. The future rad-hard FPGA will be available in space qualified package and commercial package with a clear pricing strategy to maximise product dissemination outside space markets
• Improve the overall European space technology landscape and complement the activities of European and national space programmes. VEGAS is clearly set up to complement the ongoing ESA/CNES BRAVE project
• VEGAS will have clear social and evironmental impacts by offering a very versatile technology able to meet multiple applications in various markets with the same device. It will also facilitate SMEs access to advance space applications

VEGAS will give the possibility for Europe to have free, unrestricted access to advanced rad-hard FPGA for space technology. VEGAS FPGA will meet all technology requirements specified in the Excerpt from Critical Space Technologies for European Strategic Non-Dependence List of Urgent Actions for 2012/2013 published in June 2014. Therefore VEGAS is fully compliant regarding rad-hard FPGA with the list of urgent actions for Critical Space Technologies for European Strategic Non-Dependence for the time-frame of 2012-2013.

VEGAS will give access to European space industry to the most advanced rad-hard FPGA devices without any exportation restriction. These new rad-hard FPGA will also offer unique SEE mitigation techniques and advanced features such as DPS or high speed buses. As described in the chart below, rad-hard FPGA are commonly used in satellites and these new devices will have a significant impact on future space application performance. It is even more the case for European satellite vendors which are often limited with ITAR free technologies. VEGAS is expected to have a clear impact on European space industry by improving European satellite vendors’ competiveness. VEGAS will also improve space technology dissemination to SMEs by offering a cheaper technology than advanced ASIC development. Indeed, advanced FPGA like NG-FPGA-MEDIUM and NG-FPGA-LARGE can be used instead of many ASIC which significantly reduces NRE associated to new application development.

Paper "SW-VHDL co-verification environment using open source"

Article republished by IEEE online magazine about technology transfer in the electronics sector