heteroGeneous integRated magnetic tEchnology using multifunctional standardized sTack (MSS)

Resultado final

First VerilogA model of the magnetic device to initiate the design steps

This first model, written in VerilogA to be compatible with all the standard electrical simulators, will take into account the main physical effects required to model the logic, memory, analog and RF functionalities. At this stage, the model will remain relatively generic and will be tuned later according to the progress of the technology.

Consolidated VerilogA model of the magnetic device, for optimized design

This consolidated model will be based on the preliminary model, but tuned using the characterization results of the technology, for better accuracy. A specific model card will be developped to adapt the model to this technology.

Consolidated standard cell library

The library will contain a set of Standard Cells (SC), elementary logic functions to synthetize more complex logic circuits. The variety of the cells will represent various design corners (low-power area efficient, fast, resilient cells...) and cover different output capacitive loads.

Magnetic technology files and integration in the design suite for the physical verifications

This technology files are part of a Process Design Kit (PDK) allowing to integrate the technology in the standard design suites of microelectronics. It will contain in particular : - Technology files containing the design rules provided by Spintec or Tower for Design Rules Checking, -technology files giving the informations about the technology to perform extraction of the circuit.

Management plan

This Management Plan is a mandatory deliverable of the GREAT project, but is also considered as a key feature for the management of the project. It has been designed to be the official Project Handbook for any participant to GREAT. Any project member (project managers, engineer, scientist, etc.) should read it at least once. The main management features described in this document is: 1) Management structures that describe the formal project management organization and responsibilities sharing. 2) Management processes which are working routines and practices that each person participating to the project should apply. 3) Management tools that are techniques, medium or reference documents that help the implementation of the management process.

2nd Management Periodic Report

The Management Periodic Report provides an explanation of personnel costs, subcontracting and any major costs incurred by each beneficiary, such as the purchase of important equipment, travel costs, large consumable items, etc., linking them to work packages.

Validation of the first test chip for each IP block.

This report will include all public information regarding the design of IP blocks within tasks 3.1 (Sensors) and 3.3 (MSS-controlled digital tuning circuits). MTJ-based sensors should include magnetic-field sensors for compass applications and some additional sensors that use the magnetic field as an intermediate physical magnitude. On this later principle, two applications have been identified: a voltmeter with a high galvanic isolation and an ammeter. One particular targeted IP block is a smart power-PAD that would be able to monitor the instantaneous power delivered at the better or that would be able to inform instantaneously if the delivered power goes higher than a fixed an/or programmable threshold is reached. Digital tuning circuits will include a family of analog elementary functions (voltage and current sources, OTA) that will include a non-volatile digital tuning of the main characteristic (output voltage or current, transconductance of the OTA) to replace fuse-based approach when compensating for variability. Detailed and restricted information will be given in a restricted annex.

1st Community Periodic Contribution

A report on the distribution of the European Union financial contribution between beneficiaries will be submitted after GREAT first period.

Report about demonstration of the sensor functionality using the MSS stack

This report will present the test results of the MSS stack used for sensor applications. In particular, the following performances will be evaluated: - Sensistivity of the sensor, - Linearity of the response, - Low-hysteresis.

1st Management Periodic Report

2nd Community Periodic Contribution

A 2nd report on the distribution of the European Union financial contribution between beneficiaries will be submitted after GREAT second period.

Report about demonstration of the memory functionality using the MSS stack

Report about memory functionality, with particular focus on retention versus size and ellipse aspect ratio

Report about demonstration of RF functionality using the MSS stack

Using the MSS stack, magnetic nanopillar devices will be realized and the RF functions investigated. These functions consider the emission of a microwave voltage signal, with properties that are suitable for integration into a PLL (D3.2). Other functions, such as modulation and detection will also be considered were suitable.

2nd Dissemination & Promotion of project results

The Report on dissemination and promotion of the project’s results (including socio-economic impact and target groups for the results of the research) is established on a periodic base. It is a short focus of GREAT exploitable knowledge and summarizes the activities targeting scientific community, industry and general public. It includes 3 summary tables of the dissemination and promotion activities in these 3 fields. This document aims at screening the different results partners have obtained thanks to this project and how they are willing to exploit but also disseminate it.

Final IP documentation

This report will include all public information with respect to the designed IP blocks within tasks 3.1 (Sensors) and 3.3 (MSS-controlled digital tuning circuits). Expected and/or obtained performances will be given in a form close to a data sheet for each IP blocks. Detailed and restricted information will be given in a restricted annex.

Report on Ø300mm wafer processing methodology, WiW and WtW uniformity

WiW: TMR and RA uniformity <6% @ RA=10 Ohm.µm². WtW: TMR and RA <4% @ RA=10 Ohm.µm².

Report on hybrid memory hierarchy and processor architecture design techniques providing density, performance, low power and resilience

This report will summarize the results of the hybrid memory hierarchy (Registers, FFs, caches, etc.) analysis for a variety of processor architectures (e.g. GPUs, DSPs, standard many-core microprocessors). The focus will be on resiliency, low-power, high density and performance.

GREAT website

The Partners will establish within the first 6 months a “great.eu” home page on a World Wide Web (www) server accessible via the Internet. In an area restricted to project partners and the European Commission (password protected), it will provide: the “Description of Action” for the contract, work schedules and logistics information, updates on deliverables, news and project report, issues regarding dissemination, also including abstracts of papers and presentations…

One publication on micromagnetic modelling

The publication will analyze via micromagnetic simulations the magnetic behavior of the MTJs of MSS under magnetic field and spin-polarized current.

Project Presentation

The Project Presentation is a short description of GREAT objectives, goals, approach, expected results and participants. The purpose of this document is to use it for dissemination of GREAT and all the information included here will also be included in the project web site.

Publicaciones

A 0.41 mW Band-Tunable 6th-Order IF Bandpass Filter with 40ns Settling Time in 45nm CMOS SOI

Autores: Ma, R.; Tibenszky, Z.; Kreißig, M.; Ellinger, F.
Publicado en: 2019
Editor: IEEE European Integrated Microwave Circuits Conference

A Fast Switchable and Band-Tunable 5-7.5 GHz LNA in 45nm CMOS SOI Technology

Autores: Ma, R.; Kreißig, M.; Ellinger, F.
Publicado en: 2018
Editor: IEEE International Conference on Electronics, Circuits and Systems (ICECS)

From Spintronic Devices to Hybrid CMOS/Magnetic System On Chip

Autores: Sophiane Senni, Frederic Ouattara, Jad Modad, Kaan Sevin, Guillaume Patrigeon, Pascal Benoit, Pascal Nouet, Lionel Torres, Francois Duhem, Gregory Di Pendina, Guillaume Prenat
Publicado en: 2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2018, Página(s) 188-191, ISBN 978-1-5386-4756-1
Editor: IEEE
DOI: 10.1109/VLSI-SoC.2018.8644875

GREAT: HeteroGeneous IntegRated Magnetic tEchnology Using Multifunctional Standardized sTack

Autores: Mehdi Tahoori, Sarath Mohanachandran Nair, Rajendra Bishnoi, Sophiane Senni, Jad Mohdad, Frederick Mailly, Lionel Torres, Pascal Benoit, Pascal Nouet, Rui Ma, Martin KreiBig, Frank Ellinger, Kotb Jabeur, Pierre Vanhauwaert, Gregory Di Pendina, Guillaume Prenat
Publicado en: 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2017, Página(s) 344-349, ISBN 978-1-5090-6762-6
Editor: IEEE
DOI: 10.1109/ISVLSI.2017.67

FlexNode: a reconfigurable Internet of Things node for design evaluation

Autores: Patrigeon , Guillaume; Leloup , Paul; Benoit , Pascal; Torres , Lionel
Publicado en: SAS: Sensors Applications Symposium, Edición 7, 2019
Editor: IEEE

A novel SRAM — STT-MRAM hybrid cache implementation improving cache performance

Autores: Odilia Coi, Guillaume Patrigeon, Sophiane Senni, Lionel Torres, Pascal Benoit
Publicado en: 2017 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), 2017, Página(s) 39-44, ISBN 978-1-5090-6037-5
Editor: IEEE
DOI: 10.1109/NANOARCH.2017.8053704

FPGA-Based Platform for Fast Accurate Evaluation of Ultra Low Power SoC

Autores: Guillaume Patrigeon, Pascal Benoit, Lionel Torres
Publicado en: 2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2018, Página(s) 123-128, ISBN 978-1-5386-6365-3
Editor: IEEE
DOI: 10.1109/PATMOS.2018.8464173

Post-fabrication soft trimming of resistive sensors

Autores: I. Shankhour, J. Mohdad, F. Mailly and P. Nouet
Publicado en: 2018 Symposium on Design, Test, Integration & Packaging of MEMS and MOEMS (DTIP), Roma, 2018, pp. 1-4, 2018
Editor: IEEE

Using multifunctional standardized stack as universal spintronic technology for IoT

Autores: M. Tahoori, S. M. Nair, R. Bishnoi, S. Senni, J. Mohdad, F. Mailly, L. Torres, P. Benoit, A. Gamatie, P. Nouet, F. Ouattara, G. Sassatelli, K. Jabeur, P. Vanhauwaert, A. Atitoaie, I. Firastrau, G. Di Pendina, G. Prenat
Publicado en: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018, Página(s) 931-936, ISBN 978-3-9819263-0-9
Editor: IEEE
DOI: 10.23919/date.2018.8342143

Temperature Limits of Single and Composite Storage Layer with Different Thicknesses and Capping Materials for p-STT-MRAM Applications

Autores: Luc Tillie, Jyotirmoy Chatterjee, Ricardo Sousa, Stephane Auffret, Jude Guelfucci, Etienne Nowak, Bernard Dieny, Ioan-Lucian Prejbeanu, N. Lamard
Publicado en: 2018 IEEE International Memory Workshop (IMW), 2018, Página(s) 1-4, ISBN 978-1-5386-5247-3
Editor: IEEE
DOI: 10.1109/imw.2018.8388854

P-STT-MRAM thermal stability and modeling of its temperature dependence

Autores: L. Tillie, B. Dieny, R. C. Sousa, J. Chatterjee, S. Auffret, N. Lamard, J. Guelffucci, E. Nowak, I.L. Prejbeanu
Publicado en: 2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 2018, Página(s) 1-2, ISBN 978-1-5386-4825-4
Editor: IEEE
DOI: 10.1109/vlsi-tsa.2018.8403857

Spintronic based RF components

Autores: U. Ebels, J. Hem, A. Purbawati, A. Ruiz Calafora, C. Murapaka, L. Vila, K. Jaimes Merazzo, E. Jimenez, M.-C. Cyrille, R. Ferreira, M. Kreissig, R. Ma, F. Ellinger, R. Lebrun, S. Wittrock, V. Cros, P. Bortolotti
Publicado en: 2017 Joint Conference of the European Frequency and Time Forum and IEEE International Frequency Control Symposium (EFTF/IFC), 2017, Página(s) 66-67, ISBN 978-1-5386-2916-1
Editor: IEEE
DOI: 10.1109/fcs.2017.8088802

A novel SRAM - STT-MRAM hybrid cache implementation improving cache performance

Autores: Odilia Coi, Guillaume Patrigeon, Sophiane Senni, Lionel Torres, Pascal Benoit
Publicado en: IEEE/ACM International Symposium on Nanoscale Architectures, Edición July 2017, 2017
Editor: IEEE/ACM

Embedded Systems to High Performance Computing using STT-MRAM

Autores: Sophiane Senni, Thibaud Delobelle, Odilia Coi, Pierre-Yves Peneau, Lionel Torres, Abdoulaye Gamatie, Pascal Benoit and Gilles Sassatelli
Publicado en: IEEE DATE 2017 Conference, Edición March 2017, 2017, ISSN 1558-1101
Editor: IEEE DATE
DOI: 10.23919/DATE.2017.7927046

"""Embedded MRAM to HPC Computing"". Presentation of the GREAT activities during this workshop"

Autores: Lionel Torres, Sophiane Senni
Publicado en: Edición May 2017, 2017
Editor: INRIA

"""Processor Architecture Based on MRAM"". Presentation to the emerging technologies days of the club EEA"

Autores: Lionel Torres
Publicado en: Edición October 2016, 2016
Editor: EEA

Spin torque oscillator based BFSK modulation

Autores: R. Ma, A. Purbawati, M. Kreisig, F. Protze, A. Ruiz-Calaforra, J. Hem, U. Ebels, F. Ellinger
Publicado en: 2017 13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), 2017, Página(s) 1-4, ISBN 978-1-5090-6508-0
Editor: IEEE
DOI: 10.1109/PRIME.2017.7974092

MAGNETIC RANDOM ACCESS MEMORIES: STATUS AND ROADMAP (invited talk)

Autores: I. L. Prejbeanu, R.C. Sousa, B. Dieny
Publicado en: THE 9th INTERNATIONAL CONFERENCE ON ADVANCED MATERIALS, ROCAM 2017, 2017
Editor: ROCAM

Ultrafast sub-ns MRAM concepts for cache applications (invited talk)

Autores: I. L. Prejbeanu, A. Timopheev, M. Miron, G. Gaudin, B. Lacoste, T. Devolder, M. Marins de Castro, R. C. Sousa, L. D. Buda-Prejbeanu, S. Auffret, U. Ebels, B. Rodmacq, B. Dieny
Publicado en: Joint York-Tohoku-Kaiserslautern Symposium on spintronics, 2017
Editor: York-Tohoku-Kaiserslautern Symposium

Dramatic improvement of tunneling magnetoresistance and thermal stability factor of STT-MRAM cells by replacing Ta with W/Ta cap layers (oral presentation)

Autores: Chatterjee J, Sousa R, Auffret S and Dieny B.
Publicado en: IEEE International Magnetics Conference INTERMAG Europe, 2017
Editor: IEEE, ITERMAG

Design and Evaluation of a 28-nm FD-SOI STT-MRAM for Ultra-Low Power Microcontrollers

Autores: Guillaume Patrigeon, Pascal Benoit, Lionel Torres, Sophiane Senni, Guillaume Prenat, Gregory Di Pendina
Publicado en: IEEE Access, Edición 7, 2019, Página(s) 58085-58093, ISSN 2169-3536
Editor: Institute of Electrical and Electronics Engineers Inc.
DOI: 10.1109/ACCESS.2019.2906942

Non-Volatile Processor Based on MRAM for Ultra-Low-Power IoT Devices

Autores: Sophiane Senni, Lionel Torres, Gilles Sassatelli, Abdoulaye Gamatie
Publicado en: ACM Journal on Emerging Technologies in Computing Systems, Edición 13/2, 2017, Página(s) 1-23, ISSN 1550-4832
Editor: Association for Computing Machinary, Inc.
DOI: 10.1145/3001936

Normally-Off Computing and Checkpoint/Rollback for Fast, Low-Power and Reliable Devices

Autores: Sophiane Senni, Lionel Torres, Pascal Benoit, Abdoulaye Gamatie, Gilles Sassatelli
Publicado en: IEEE Magnetics Letters, Edición 2017-07-19, 2017, Página(s) 1-1, ISSN 1949-307X
Editor: Institute of Electrical and Electronics Engineers
DOI: 10.1109/LMAG.2017.2712780

"Magnetic Random&;#x02010;Access Memory"

Autores: Bernard Dieny, I. Lucian Prejbeanu
Publicado en: "Introduction to Magnetic Random&;#x02010;Access Memory", 2017, Página(s) 101-164, ISBN 9781-119079415
Editor: "John Wiley &;#38; Sons, Inc."
DOI: 10.1002/9781119079415.ch5

Micromagnetism Applied to Magnetic Nanostructures

Autores: Liliana D. Buda&xPrejbeanu
Publicado en: "Introduction to Magnetic Random&;#x02010;Access Memory", 2017, Página(s) 55-78, ISBN 9781-119079415
Editor: "John Wiley &;#38; Sons, Inc."
DOI: 10.1002/9781119079415.ch3

Multifunctional magnetic tunnel junction standardized stack as universal spintronic technology for IoT

Autores: A. Chavent, V. Iurchuk, L.Tillie, Y. Bel, L. Vila, U. Ebels R. Sousa B. Dieny, G. di Pendina, G. Prenat, J. Langer, J. Wrona, I. L. Prejbeanu
Publicado en: Special MRAM poster session at IEDM, poster presentation, 2018
Editor: IEDM

A multifunctional standardized MTJ stack embedding sensor, memory and oscillator functionalities

Autores: Antoine Chavent, Vadym Iurchuk, Luc Tillie, Yoann Bel, Nathalie Lamard, Laurent Vila, Ursula Ebels, Ricardo C. Sousa, Bernard Dieny, Gregory Di Pendina, Guillaume Prenat, Juergen Langer, Jerzy Wrona, Ioan Lucian Prejbeanu
Publicado en: Oral presentation at JEMS 2019, 2019
Editor: JEMS

Organisation of Special session at DATE Conference : Organisation of the Special session about « Hot Topic Session: Spintronics-based Computing » at IEEE DATE Conference.

Autores: LIRMM & KIT (2 papers accepted)
Publicado en: DATE 2017, 2017
Editor: IEEE

"Special joint poster session on MRAM at IEDM ""Non-volatile Processor Based on STT-MRAM"""

Autores: Sophiane Senni, Lionel Torres
Publicado en: IEDM, Edición 5-7 Dec 2016, 2016
Editor: IEDM

"Speaker at InMRAM 2017: introductory Course on Magnetic Random Access Memory – Talk based on the GREAT Results ""Beyond MRAM - CMOS/Mag Integrated Circuit"""

Autores: L. Torres
Publicado en: Edición 3-5 july 2017, 2017
Editor: LIRMM

Objets Communicants pour leS EnvironnementS et le Vivant

Autores: P. Nouet
Publicado en: Edición 3 et 4 juillet 2017, 2017
Editor: CNRS

"'Simulation and Evaluation of Heterogeneous Embedded Multicore Architectures"". Invited talk at FETCH 2017 (Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes Embarqués Hétérogènes)"

Autores: Abdoulaye Gamatié
Publicado en: Edición January 2017, 2017
Editor: FETCH

Shape effects on magnetization states of fully perpendicular spin transfer torque nano-oscillators (poster)

Autores: Alexandru Atitoaie(1), Marius Volmer(1), Liliana Buda-Prejbeanu(2,3,4), Ursula Ebels(2,3,4), Ioana Firastrau(1), (1)Transilvania University of Brasov, 500036, Brasov, Romania, (2)Univ. Grenoble Alpes, F-38000, Grenoble, France, (3)CEA, INAC – SPINTEC, F-38000, Grenoble, France, (4) CNRS, SPINTEC, F-38000, Grenoble, France
Publicado en: 11th International Symposium on Hysteresis Modeling and Micromagnetism, 2017
Editor: HMM

Phase diagrams study of spin transfer torque nano-oscillators based on fully perpendicular magnetic tunnel junctions (poster)

Effect of bottom electrode smoothness on tunnel magnetoresistance in top pinned perpendicular magnetic tunnel junctions (poster)

Autores: J. Wrona, J. Langer, S. Tibus, B. Ocker, J. Kanak, M. Cecot, T. Stobiecki
Publicado en: 13th Joint MMM-Intermag Conference, 2016
Editor: MMM-Intermag

High temperature stable bottom pinned perpendicular magnetic tunnel junctions (poster)

Autores: J. Wrona, J. Langer, S. Tibus, B. Ocker
Publicado en: IEDM special poster session on MRAM, 2016
Editor: IEEE International Electron Devices Meeting (IEDM)

Macrospin characterization of fully perpendicular spin transfer torque nano-oscillators (oral presentation)

Autores: Alexandru Atitoaie(1), Marius Volmer(1), Liliana D. Buda-Prejbeanu(2,3,4), Ursula Ebels(2,3,4), Ioana Firastrau(1), (1)Transilvania University of Brasov, 500036, Brasov, Romania, (2)Univ. Grenoble Alpes, F-38000, Grenoble, France, (3)CEA, INAC – SPINTEC, F-38000, Grenoble, France, (4) CNRS, SPINTEC, F-38000, Grenoble, France
Publicado en: The 9th International Conference on Advanced Materials, ROCAM2017, 2017
Editor: ROCAM

High temperature stable bottom pinned perpendicular magnetic tunnel junctions (poster)

Autores: J. Wrona, M. Zhu, J. Langer, S. Tibus, M. Smalley, S. Bennett, B. Ocker
Publicado en: 61th Annual Conference on Magnetism and Magnetic Materials, 2016
Editor: MMM

High Volume Production of pTMR Layer Stacks for MRAM and Sensor Applications (invited oral presentation)

Autores: Jürgen Langer
Publicado en: Fraunhofer IPMS - CNT Industry Partner Day Innovative: Modules for IoT, 2016
Editor: Fraunhofer IPMS

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