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A Universal Micro-Server Ecosystem by Exceeding the Energy and Performance Scaling Boundaries

Deliverables

Hypervisor with Error Handling Capabilities

Hypervisor with Error Handling Capabilities

OS Support for Standalone Micro-Server Deployments

OS Support for Standalone Micro-Server Deployments

OpenStack Support for UniServer

OpenStack Support for UniServer

Benchmark Suite for StressLog

Benchmark Suite for StressLog

OpenStack Resilience on Extended Margins Micro-Servers

OpenStack Resilience on Extended Margins Micro-Servers

Error-Resilient Hypervisor

Error-Resilient Hypervisor

HEI and Error Handlers Implementation

HEI and Error Handlers Implementation

2nd Report on Hypervisor / System Software Interface

2nd Report on Hypervisor / System Software Interface

Secure Access- Control Design for Stored Margin Values

Secure Access- Control Design for Stored Margin Values

Countermeasures to Security Risks due to Extended Margins

Countermeasures to Security Risks due to Extended Margins

2nd Vertical, Full System Integration, and Validation

2nd Vertical, Full System Integration, and Validation

1st Analysis of Processor Cores under Various Stress Conditions

1st Analysis of Processor Cores under Various Stress Conditions

2nd Report on Metrics of Success Against State-of-the- Art

2nd Report on Metrics of Success Against State-of-the-Art

1st Report on Metrics of Success Against State-of-the-Art

Report on Metrics of Success Against State-of-the-Art

1st Report on Hypervisor / System Software Interface

1st Report on Hypervisor / System Software Interface

Data Management Plan and Gender Considerations

Data Management Plan and Gender Considerations

1st Evaluation of the Prototype and Comparison to State-of-the- Art in terms of Energy, Security and Determined Metrics of Success

1st Evaluation of the Prototype and Comparison to State-of-the-Art in terms of Energy, Security and Determined Metrics of Success

Resource Management Policies in the Hypervisor

Resource Management Policies in the Hypervisor

1st Vertical, Full System Integration, and Validation

1st Vertical, Full System Integration, and Validation

2nd Analysis of Processor Cores under Various Stress Conditions

2nd Analysis of Processor Cores under Various Stress Conditions

End-to-end UniServer TCO Analysis and Time-Dependent Performance Degradation

End-to-end UniServer TCO Analysis and Time-Dependent Performance Degradation

Definition of the UniServer board

Definition of the UniServer board

1st Analysis of On-Chip Caches and Dynamic Memories

1st Analysis of On-Chip Caches and Dynamic Memories

2nd Analysis of On- Chip Caches and Dynamic Memories

2nd Analysis of On-Chip Caches and Dynamic Memories

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Publications

Variation-Aware Pipelined Cores through Path Shaping and Dynamic Cycle Adjustment: Case Study on a Floating-Point Unit

Author(s): Tsiokanos, I., Mukhanov, L., Nikolopoulos, D., & Karakonstantis, G
Published in: Proceeding of the International Symposium on Low Power Electronics 2018, 2018

Minimization of Timing Failures in Pipelined Designs via Path Shaping and Operand Truncation

Author(s): Ioannis Tsiokanos, Lev Mukhanov, Dimitrios S. Nikolopoulos, Georgios Karakonstantis
Published in: 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS), 2018, Page(s) 171-176
DOI: 10.1109/iolts.2018.8474084

An energy-efficient and error-resilient server ecosystem exceeding conservative scaling limits

Author(s): Georgios Karakonstantis, Konstantinos Tovletoglou, Lev Mukhanov, Hans Vandierendonck, Dimitrios S. Nikolopoulos, Peter Lawthers, Panos Koutsovasilis, Manolis Maroudas, Christos D. Antonopoulos, Christos Kalogirou, Nikos Bellas, Spyros Lalis, Srikumar Venugopal, Arnau Prat-Perez, Alejandro Lampropulos, Marios Kleanthous, Andreas Diavastos, Zacharias Hadjilambrou, Panagiota Nikolaou, Yiannakis Sazei
Published in: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018, Page(s) 1099-1104
DOI: 10.23919/date.2018.8342175

Relaxing DRAM refresh rate through access pattern scheduling: A case study on stencil-based algorithms

Author(s): Konstantinos Tovletoglou, Dimitrios S. Nikolopoulos, Georgios Karakonstantis
Published in: 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS), 2017, Page(s) 45-50
DOI: 10.1109/iolts.2017.8046197

Characterization of HPC workloads on an ARMv8 based server under relaxed DRAM refresh and thermal stress

Author(s): Lev Mukhanov, Konstantinos Tovletoglou, Dimitrios S. Nikolopoulos, Georgios Karakonstantis
Published in: Proceedings of the 18th International Conference on Embedded Computer Systems Architectures, Modeling, and Simulation - SAMOS '18, 2018, Page(s) 230-235
DOI: 10.1145/3229631.3236091

Userspace Hypervisor Data Characterization in Virtualized Environment

Author(s): Bin Wang, Hans Vandierendonck, Georgios Karakonstantis, Dimitrios S. Nikolopoulos
Published in: 2018 IEEE 24th International Conference on Parallel and Distributed Systems (ICPADS), 2018, Page(s) 638-645
DOI: 10.1109/padsw.2018.8644612

Low-Power Variation-Aware Cores based on Dynamic Data-Dependent Bitwidth Truncation

Author(s): Ioannis Tsiokanos, Lev Mukhanov, Georgios Karakonstantis
Published in: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2019, Page(s) 698-703
DOI: 10.23919/date.2019.8714942

DRAM Characterization under Relaxed Refresh Period Considering System Level Effects within a Commodity Server

Author(s): Lev Mukhanov, Konstantinos Tovletoglou, Dimitrios S. Nikolopoulos, Georgios Karakonstantis
Published in: 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS), 2018, Page(s) 236-239
DOI: 10.1109/iolts.2018.8474184

Measuring and Exploiting Guardbands of Server-Grade ARMv8 CPU Cores and DRAMs

Author(s): Konstantinos Tovletoglou, Lev Mukhanov, Georgios Karakonstantis, Athanasios Chatzidimitriou, George Papadimitriou, Manolis Kaliorakis, Dimitris Gizopoulos, Zacharias Hadjilambrou, Yiannakis Sazeides, Alejandro Lampropulos, Shidhartha Das, Phong Vo
Published in: 2018 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W), 2018, Page(s) 6-9
DOI: 10.1109/dsn-w.2018.00013

Frequency and time domain analysis of power delivery network for monolithic 3D ICs

Author(s): Kyungwook Chang, Shidhartha Das, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
Published in: 2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2017, Page(s) 1-6
DOI: 10.1109/ISLPED.2017.8009180

A System-Level Voltage/Frequency Scaling Characterization Framework for Multicore CPUs

Author(s): G.Papadimitriou, M.Kaliorakis, A.Chatzidimitriou, D.Gizopoulos (U Athens), G.Favor, K.Sankaran and S.Das
Published in: 13th IEEE Workshop on Silicon Errors in Logic – System Effects 2017 (SELSE 2017), 2017

MeRLiN - Exploiting Dynamic Instruction Behavior for Fast and Accurate Microarchitecture Level Reliability Assessment

Author(s): Manolis Kaliorakis, Dimitris Gizopoulos, Ramon Canal, Antonio Gonzalez
Published in: Proceedings of the 44th Annual International Symposium on Computer Architecture - ISCA '17, Issue 1, 2017, Page(s) 241-254
DOI: 10.1145/3079856.3080225

A Methodology for Oracle Selection of Monitors and Knobs for Configuring an HPC System running a Flood Management Application

Author(s): Panagiota Nikolaou, Yiannakis Sazeides, Antoni Portero, Radim Vavřík and Vit Vondrak
Published in: 5th Workshop on High Performance Energy Efficient Embedded Systems, 2017, Page(s) 6

Harnessing Voltage Margins for Energy Efficiency in Multicore CPUs

Author(s): George Papadimitriou, Manolis Kaliorakis, Athanasios Chatzidimitriou, DImitris Gizopoulos
Published in: IEE/ACM International Symposium on Microarchitecture (MICRO 2017), Issue 1, 2017

How to make SMT Tail Latency Friendly

Author(s): Zacharias Hadjilambrou, Yannakis Sazeides,
Published in: Energy-efficient Servers for Cloud and Edge Computing 2017 Workshop (ENeSCE 2017), 2017

Access-aware DRAM failure-rate estimation under relaxed refresh operations

Author(s): Konstantinos Tovletoglou, Dimitrios S. Nikolopoulos, Georgios Karakonstantis
Published in: 2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2017, Page(s) 292-299
DOI: 10.1109/samos.2017.8344643

Towards a property graph generator for benchmarking

Author(s): Arnau Prat-Pérez, Joan Guisado-Gámez, Xavier Fernández Salas, Petr Koupy, Siegfried Depner, Davide Basilio Bartolini
Published in: Proceedings of the Fifth International Workshop on Graph Data-management Experiences & Systems - GRADES'17, 2017, Page(s) 1-6
DOI: 10.1145/3078447.3078453

RT Level vs. Microarchitecture-Level Reliability Assessment: Case Study on ARM(R) Cortex(R)-A9 CPU

Author(s): Athanasios Chatzidimitriou, Manolis Kaliorakis, Dimitris Gizopoulos, Maurizio Iacaruso, Mauro Pipponzi, Riccardo Mariani, Stefano Di Carlo
Published in: 2017 47th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W), 2017, Page(s) 117-120
DOI: 10.1109/DSN-W.2017.16

Voltage margins identification on commercial x86-64 multicore microprocessors

Author(s): George Papadimitriou, Manolis Kaliorakis, Athanasios Chatzidimitriou, Charalampos Magdalinos, Dimitris Gizopoulos
Published in: 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS), 2017, Page(s) 51-56
DOI: 10.1109/iolts.2017.8046198

On the Evaluation of the Total-Cost-of-Ownership Trade-offs in Edge vs Cloud deployments: A Wireless-Denial-of-Service Case Study

Author(s): Panagiota Nikolaou, Yiannakis Sazeides, Alejandro Lampropoulos, Denis Guilhot, Andrea Bartoli, George Papadimitriou, Athanasios Chatzidimitriou, Dimitris Gizopoulos, Konstantinos Tovletoglou, Lev Mukhanov, Georgios Karakonstantis
Published in: IEEE Transactions on Sustainable Computing, 2019, Page(s) 1-1, ISSN 2377-3782
DOI: 10.1109/tsusc.2019.2894018

Significance-Driven Data Truncation for Preventing Timing Failures

Author(s): Ioannis Tsiokanos, Lev Mukhanov, Dimitrios S. Nikolopoulos, Georgios Karakonstantis
Published in: IEEE Transactions on Device and Materials Reliability, Issue 19/1, 2019, Page(s) 25-36, ISSN 1530-4388
DOI: 10.1109/tdmr.2019.2898949

Power Integrity Analysis of a 28 nm Dual-Core ARM Cortex-A57 Cluster Using an All-Digital Power Delivery Monitor

Author(s): Paul N. Whatmough, Shidhartha Das, Zacharias Hadjilambrou, David M. Bull
Published in: IEEE Journal of Solid-State Circuits, Issue 52/6, 2017, Page(s) 1643-1654, ISSN 0018-9200
DOI: 10.1109/JSSC.2017.2669025

DARE: Data-Access Aware Refresh via spatial-temporal application resilience on commodity servers

Author(s): Charalampos Chalios, Giorgis Georgakoudis, Konstantinos Tovletoglou, George Karakonstantis, Hans Vandierendonck, Dimitrios S Nikolopoulos
Published in: The International Journal of High Performance Computing Applications, 2017, Page(s) 109434201771861, ISSN 1094-3420
DOI: 10.1177/1094342017718612