A Universal Micro-Server Ecosystem by Exceeding the Energy and Performance Scaling Boundaries

Informazioni relative al progetto

UniServer

ID dell’accordo di sovvenzione: 688540

DOI

10.3030/688540

Progetto chiuso

Data della firma CE 9 Dicembre 2015

Data di avvio 1 Febbraio 2016

Data di completamento 31 Luglio 2019

Finanziato da

• INDUSTRIAL LEADERSHIP - Leadership in enabling and industrial technologies - Information and Communication Technologies (ICT)

Costo totale

€ 4 815 810,00

Contributo UE

€ 4 815 810,00

Coordinato da

THE QUEEN'S UNIVERSITY OF BELFAST
United Kingdom

CORDIS fornisce collegamenti ai risultati finali pubblici e alle pubblicazioni dei progetti ORIZZONTE.

I link ai risultati e alle pubblicazioni dei progetti del 7° PQ, così come i link ad alcuni tipi di risultati specifici come dataset e software, sono recuperati dinamicamente da .OpenAIRE .

Risultati finali

Other (7)

Hypervisor with Error Handling Capabilities
OS Support for Standalone Micro-Server Deployments
OpenStack Support for UniServer
Benchmark Suite for StressLog
OpenStack Resilience on Extended Margins Micro-Servers
Error-Resilient Hypervisor
HEI and Error Handlers Implementation

Documents, reports (17)

2nd Report on Hypervisor / System Software Interface
Secure Access- Control Design for Stored Margin Values
Countermeasures to Security Risks due to Extended Margins
2nd Vertical, Full System Integration, and Validation
1st Analysis of Processor Cores under Various Stress Conditions
2nd Report on Metrics of Success Against State-of-the- Art

2nd Report on Metrics of Success Against State-of-the-Art

1st Report on Metrics of Success Against State-of-the-Art

Report on Metrics of Success Against State-of-the-Art

1st Report on Hypervisor / System Software Interface
Data Management Plan and Gender Considerations
1st Evaluation of the Prototype and Comparison to State-of-the- Art in terms of Energy, Security and Determined Metrics of Success

1st Evaluation of the Prototype and Comparison to State-of-the-Art in terms of Energy, Security and Determined Metrics of Success

Resource Management Policies in the Hypervisor
1st Vertical, Full System Integration, and Validation
2nd Analysis of Processor Cores under Various Stress Conditions
End-to-end UniServer TCO Analysis and Time-Dependent Performance Degradation
Definition of the UniServer board
1st Analysis of On-Chip Caches and Dynamic Memories
2nd Analysis of On- Chip Caches and Dynamic Memories

2nd Analysis of On-Chip Caches and Dynamic Memories

Demonstrators, pilots, prototypes (1)

Predictive Failure Module Evaluation

Pubblicazioni

Conference proceedings (19)

Variation-Aware Pipelined Cores through Path Shaping and Dynamic Cycle Adjustment: Case Study on a Floating-Point Unit

Autori: Tsiokanos, I., Mukhanov, L., Nikolopoulos, D., & Karakonstantis, G
Pubblicato in: Proceeding of the International Symposium on Low Power Electronics 2018, 2018
Editore: ISPLED

Minimization of Timing Failures in Pipelined Designs via Path Shaping and Operand Truncation

Autori: Ioannis Tsiokanos, Lev Mukhanov, Dimitrios S. Nikolopoulos, Georgios Karakonstantis
Pubblicato in: 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS), 2018, Pagina/e 171-176, ISBN 978-1-5386-5992-2
Editore: IEEE
DOI: 10.1109/iolts.2018.8474084

An energy-efficient and error-resilient server ecosystem exceeding conservative scaling limits

Autori: Georgios Karakonstantis, Konstantinos Tovletoglou, Lev Mukhanov, Hans Vandierendonck, Dimitrios S. Nikolopoulos, Peter Lawthers, Panos Koutsovasilis, Manolis Maroudas, Christos D. Antonopoulos, Christos Kalogirou, Nikos Bellas, Spyros Lalis, Srikumar Venugopal, Arnau Prat-Perez, Alejandro Lampropulos, Marios Kleanthous, Andreas Diavastos, Zacharias Hadjilambrou, Panagiota Nikolaou, Yiannakis Sazei
Pubblicato in: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018, Pagina/e 1099-1104, ISBN 978-3-9819263-0-9
Editore: IEEE
DOI: 10.23919/date.2018.8342175

Relaxing DRAM refresh rate through access pattern scheduling: A case study on stencil-based algorithms

Autori: Konstantinos Tovletoglou, Dimitrios S. Nikolopoulos, Georgios Karakonstantis
Pubblicato in: 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS), 2017, Pagina/e 45-50, ISBN 978-1-5386-0352-9
Editore: IEEE
DOI: 10.1109/iolts.2017.8046197

Characterization of HPC workloads on an ARMv8 based server under relaxed DRAM refresh and thermal stress

Autori: Lev Mukhanov, Konstantinos Tovletoglou, Dimitrios S. Nikolopoulos, Georgios Karakonstantis
Pubblicato in: Proceedings of the 18th International Conference on Embedded Computer Systems Architectures, Modeling, and Simulation - SAMOS '18, 2018, Pagina/e 230-235, ISBN 9781-450364942
Editore: ACM Press
DOI: 10.1145/3229631.3236091

Userspace Hypervisor Data Characterization in Virtualized Environment

Autori: Bin Wang, Hans Vandierendonck, Georgios Karakonstantis, Dimitrios S. Nikolopoulos
Pubblicato in: 2018 IEEE 24th International Conference on Parallel and Distributed Systems (ICPADS), 2018, Pagina/e 638-645, ISBN 978-1-5386-7308-9
Editore: IEEE
DOI: 10.1109/padsw.2018.8644612

Low-Power Variation-Aware Cores based on Dynamic Data-Dependent Bitwidth Truncation

Autori: Ioannis Tsiokanos, Lev Mukhanov, Georgios Karakonstantis
Pubblicato in: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2019, Pagina/e 698-703, ISBN 978-3-9819263-2-3
Editore: IEEE
DOI: 10.23919/date.2019.8714942

DRAM Characterization under Relaxed Refresh Period Considering System Level Effects within a Commodity Server

Autori: Lev Mukhanov, Konstantinos Tovletoglou, Dimitrios S. Nikolopoulos, Georgios Karakonstantis
Pubblicato in: 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS), 2018, Pagina/e 236-239, ISBN 978-1-5386-5992-2
Editore: IEEE
DOI: 10.1109/iolts.2018.8474184

Measuring and Exploiting Guardbands of Server-Grade ARMv8 CPU Cores and DRAMs

Autori: Konstantinos Tovletoglou, Lev Mukhanov, Georgios Karakonstantis, Athanasios Chatzidimitriou, George Papadimitriou, Manolis Kaliorakis, Dimitris Gizopoulos, Zacharias Hadjilambrou, Yiannakis Sazeides, Alejandro Lampropulos, Shidhartha Das, Phong Vo
Pubblicato in: 2018 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W), 2018, Pagina/e 6-9, ISBN 978-1-5386-6553-4
Editore: IEEE
DOI: 10.1109/dsn-w.2018.00013

Frequency and time domain analysis of power delivery network for monolithic 3D ICs

Autori: Kyungwook Chang, Shidhartha Das, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
Pubblicato in: 2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2017, Pagina/e 1-6, ISBN 978-1-5090-6023-8
Editore: IEEE
DOI: 10.1109/ISLPED.2017.8009180

A System-Level Voltage/Frequency Scaling Characterization Framework for Multicore CPUs

Autori: G.Papadimitriou, M.Kaliorakis, A.Chatzidimitriou, D.Gizopoulos (U Athens), G.Favor, K.Sankaran and S.Das
Pubblicato in: 13th IEEE Workshop on Silicon Errors in Logic – System Effects 2017 (SELSE 2017), 2017
Editore: IEEE

MeRLiN - Exploiting Dynamic Instruction Behavior for Fast and Accurate Microarchitecture Level Reliability Assessment

Autori: Manolis Kaliorakis, Dimitris Gizopoulos, Ramon Canal, Antonio Gonzalez
Pubblicato in: Proceedings of the 44th Annual International Symposium on Computer Architecture - ISCA '17, Numero 1, 2017, Pagina/e 241-254, ISBN 9781-450348928
Editore: ACM Press
DOI: 10.1145/3079856.3080225

A Methodology for Oracle Selection of Monitors and Knobs for Configuring an HPC System running a Flood Management Application

Autori: Panagiota Nikolaou, Yiannakis Sazeides, Antoni Portero, Radim Vavřík and Vit Vondrak
Pubblicato in: 5th Workshop on High Performance Energy Efficient Embedded Systems, 2017, Pagina/e 6
Editore: HiPEAC

Harnessing Voltage Margins for Energy Efficiency in Multicore CPUs

Autori: George Papadimitriou, Manolis Kaliorakis, Athanasios Chatzidimitriou, DImitris Gizopoulos
Pubblicato in: IEE/ACM International Symposium on Microarchitecture (MICRO 2017), Numero 1, 2017
Editore: IEEE/ACM

How to make SMT Tail Latency Friendly

Autori: Zacharias Hadjilambrou, Yannakis Sazeides,
Pubblicato in: Energy-efficient Servers for Cloud and Edge Computing 2017 Workshop (ENeSCE 2017), 2017
Editore: HiPEAC

Access-aware DRAM failure-rate estimation under relaxed refresh operations

Autori: Konstantinos Tovletoglou, Dimitrios S. Nikolopoulos, Georgios Karakonstantis
Pubblicato in: 2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2017, Pagina/e 292-299, ISBN 978-1-5386-3437-0
Editore: IEEE
DOI: 10.1109/samos.2017.8344643

Towards a property graph generator for benchmarking

Autori: Arnau Prat-Pérez, Joan Guisado-Gámez, Xavier Fernández Salas, Petr Koupy, Siegfried Depner, Davide Basilio Bartolini
Pubblicato in: Proceedings of the Fifth International Workshop on Graph Data-management Experiences & Systems - GRADES'17, 2017, Pagina/e 1-6, ISBN 9781450350389
Editore: ACM Press
DOI: 10.1145/3078447.3078453

RT Level vs. Microarchitecture-Level Reliability Assessment: Case Study on ARM(R) Cortex(R)-A9 CPU

Autori: Athanasios Chatzidimitriou, Manolis Kaliorakis, Dimitris Gizopoulos, Maurizio Iacaruso, Mauro Pipponzi, Riccardo Mariani, Stefano Di Carlo
Pubblicato in: 2017 47th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W), 2017, Pagina/e 117-120, ISBN 978-1-5386-2272-8
Editore: IEEE
DOI: 10.1109/DSN-W.2017.16

Voltage margins identification on commercial x86-64 multicore microprocessors

Autori: George Papadimitriou, Manolis Kaliorakis, Athanasios Chatzidimitriou, Charalampos Magdalinos, Dimitris Gizopoulos
Pubblicato in: 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS), 2017, Pagina/e 51-56, ISBN 978-1-5386-0352-9
Editore: IEEE
DOI: 10.1109/iolts.2017.8046198

Peer reviewed articles (4)

On the Evaluation of the Total-Cost-of-Ownership Trade-offs in Edge vs Cloud deployments: A Wireless-Denial-of-Service Case Study

Autori: Panagiota Nikolaou, Yiannakis Sazeides, Alejandro Lampropoulos, Denis Guilhot, Andrea Bartoli, George Papadimitriou, Athanasios Chatzidimitriou, Dimitris Gizopoulos, Konstantinos Tovletoglou, Lev Mukhanov, Georgios Karakonstantis
Pubblicato in: IEEE Transactions on Sustainable Computing, 2019, Pagina/e 1-1, ISSN 2377-3782
Editore: IEEE
DOI: 10.1109/tsusc.2019.2894018

Significance-Driven Data Truncation for Preventing Timing Failures

Autori: Ioannis Tsiokanos, Lev Mukhanov, Dimitrios S. Nikolopoulos, Georgios Karakonstantis
Pubblicato in: IEEE Transactions on Device and Materials Reliability, Numero 19/1, 2019, Pagina/e 25-36, ISSN 1530-4388
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tdmr.2019.2898949

Power Integrity Analysis of a 28 nm Dual-Core ARM Cortex-A57 Cluster Using an All-Digital Power Delivery Monitor

Autori: Paul N. Whatmough, Shidhartha Das, Zacharias Hadjilambrou, David M. Bull
Pubblicato in: IEEE Journal of Solid-State Circuits, Numero 52/6, 2017, Pagina/e 1643-1654, ISSN 0018-9200
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/JSSC.2017.2669025

DARE: Data-Access Aware Refresh via spatial-temporal application resilience on commodity servers

Autori: Charalampos Chalios, Giorgis Georgakoudis, Konstantinos Tovletoglou, George Karakonstantis, Hans Vandierendonck, Dimitrios S Nikolopoulos
Pubblicato in: The International Journal of High Performance Computing Applications, 2017, Pagina/e 109434201771861, ISSN 1094-3420
Editore: SAGE Publications
DOI: 10.1177/1094342017718612