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Integrated Circuit Design for Signal Processing

Objective

The INCIDE Working Group focuses first on new circuit design concepts which implies more granular on-chip communication scheme, and their applicability to the implementation of signal processing algorithms. Within INCIDE it is aimed to develop and explore design concepts based on self-timing, micropipeline architectures, and asynchronous data processing techniques. In order to achieve competitve circuit design concepts, questions related to design automation and testability are taken into account as well.

Secondly, new BiCMOS circuit concepts will be studied through realising macro building blocks, in order to evaluate the potential of BiCMOS versus CMOS.
Research for circuit design for signal processing was pursued in 2 areas: in order to overcome synchronization problems on the chip, asynchronous circuit concepts were discussed in detail and test vehicles implemented; complementary metal oxide semiconductor (CMOS) versus BCMOS was studied realizing various macro building blocks.

Concerning the design of asynchronous circuits, low level circuit design and building blocks in micropipeline architecture were studied. Improvements have been achieved in the design of handshake circuitry. Major properties of the developed circuits are relaxed timing constraints and therefore improved reliability.

Some efforts were made to apply design automation techniques (ie standard cell methodology) to the design of asynchronous circuits. This led to the development of a standard cell library consisting of DCVSL functional cells and handshake circuitry, respectively. The well known scan path technique was introduced to assure for testability. Appropriate cells were designed and added to the library to allow for the implementation of scan paths together with self timed modules and building blocks. 2 self timed test circuits, a serial parallel multiplier and a Booth multiplier with scan path were designed and successfully tested.

Novel BCMOS circuit concepts for interchip communication tunable filters and for a logic level converter ECL to CMMOS have been developed. Prototypes and test results are available.
ACTIVITIES

Within INCIDE a team was established which concentrates on asynchronous circuit concepts. Currently researchers located at the University of Ulm (Germany), Abteilung Allgemeine Elektrotechnik und Mikroelektronik, and at the Technical University of Berlin (Germany), Institut fuer Mikroelektronik, are involved. Prof. T. G. Noll from RWTH-Aachen (Germany) and Prof. D. Mueller from the Technical University of Chemnitz (Germany) are planning to participate in these activities. Besides the exchange of ideas and solutions cultivated by the members of the Group and the team, a cooperation with members of the ACID Working Group (7225) was brought about, eg visits and presentations at Workshops held by ACID-WG.

POTENTIAL

Advanced concepts for asynchronous circuits, design automation, and design for testability are considered as a whole, in order to develop suitable solutions. These are fundamental prerequisites to bring new circuit design concepts into industrial use. First results will be presented to a broad audience on ESSCIRC 1993.

Topic(s)

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Call for proposal

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Funding Scheme

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Coordinator

UNIVERSITÄT ULM
Address
Oberer Eselsberg
89081 Ulm
Germany
 

Participants (4)

NEDERLANDSE PHILIPS BEDRIJVEN BV
Netherlands
Address
Kastanjelaan, 1218
5600 MD Eindhoven
 
TECHNISCHE UNIVERSITEIT DELFT
Netherlands
Address
Mekelweg 4, 5031
2600 AG Delft
 
TECHNISCHE UNIVERSITÄT BERLIN
Germany
Address
Salzufer 17-19
10587 Berlin
 
Università degli Studi di Pavia
Italy
Address
Piazza Botta 10
27100 Pavia