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Ultra-Low PoweR technologIes and MEmory architectures for IoT

Periodic Reporting for period 1 - PRIME (Ultra-Low PoweR technologIes and MEmory architectures for IoT)

Reporting period: 2015-12-01 to 2017-03-31

The goal of the PRIME project is to establish an open Ultra Low Power (ULP) Technology Platform containing all necessary design and architecture blocks and components which could enable the European industry to increase and strengthen their competitive and leading eco-system and benefit from market opportunities created by the Internet of Things (IoT) revolution.
Over 3 years the project will develop and demonstrate the key building blocks of IoT ULP systems driven by the applications in the medical, agricultural, domestics and security domains. This will include development of high performance, energy efficient and cost effective technology platform, flexible design ecosystem (including IP and design flow), changes in architectural and power management to reduced energy consumption, security blocks based on PUF and finally the System of Chip and System in Package memory banks and processing implementations for IoT sensor node systems.
• Developped advanced as 22nm FDSOI low power technologies with logic, RF, first analog functionality.
• Embedded new memory components (STT RAM for 22-FDSOI and RRAM for 28 SLP)
• innovative design and system architecture solutions will be used to build macros and demonstrate functionality and power reduction advantage of the new IoT device components.

The PRIME project will realize several demonstrators of IoT system building blocks to show the proposed low power wireless solutions, functionality and performance of delivered design and technology blocks.
The consortium semiconductor ecosystem (IDMs, design houses, R&D, tools & wafer suppliers, foundries, system/product providers) covers complementarily all desired areas of expertise to achieve the project goals.
The project will enable an increase in Europe’s innovation capability in the area of ULP Technology, design and applications, creation of a competitive European eco-system and help to identify market leadership opportunities in security, mobility, healthcare and smart cost competitive manufacturing.
The functional demonstrators for the validation of a cost efficient technology platform (Object 1) are not yet ready, significant coordination effort has been put in place between imec-ST and imec-FhG to overcome project changes. After an initial imec-FhG technology assessment and screening of architectural options, design activity in FhG is started. The feasibility of a imec-ST design will be evaluated in October 2017. On the other hand the technology foundation of the hardware platform (Objective 2) is progressing according to (or even ahead of) schedule. On the logic side, FDSOI technology is fully qualified for mass production offering a comfortable choice of device flavors with back bias functionality. On the memory side, a high performance RRAM stack capable of delivering the target I.o.T reliability specifications have been demonstrated at device level using a realistic and production-friendly integration flow. In the case of STT-MRAM memory, at material level, the thermal stability issue and BEOL process compatibility (etch, CMP) have been addresses, paving the way for an co-integration in 22 FDSOI from summer 2017. Moving up to the system level (Objective 3) several progress have been made. For Power management related aspects, starting from an initial study of design usecases (made by imec-NL and synopsis), a simulation environment (based on the GEM5 platform) was put in place to evaluate different memory organizations. Surecore performed the analysis to benchmark the performances achieved by different memory option (using SRAM vs MRAM vs RRAM) with respect to the Power Performance Area figure of merit. For I.o.T. security related aspects Intrinisc-ID investigated the main constraints to implement a security layer in IoT devices and identified the main IoT security threats. Following this preliminary study, an assessment of the viability of commercially available SRAM device as PUF was performed while, at the same time, exploring the use ReRAM as potential PUF technology based on literature and within project (WP3) data. On a different track, concerning the design of Ultra-low-power wireless sensor, progress has been achieved with architectural evaluation, test board design and layout...