Ultra-Low PoweR technologIes and MEmory architectures for IoT

Project Information

PRIME

Grant agreement ID: 692519

DOI

10.3030/692519

Project closed

EC signature date 4 May 2016

Start date 1 December 2015

End date 30 September 2019

Funded under

• INDUSTRIAL LEADERSHIP - Leadership in enabling and industrial technologies - Information and Communication Technologies (ICT)

Total cost

€ 38 296 264,00

EU contribution

€ 12 038 776,58

Coordinated by

INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM
Belgium

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Links to deliverables and publications from FP7 projects, as well as links to some specific result types such as dataset and software, are dynamically retrieved from OpenAIRE .

Deliverables

Other (2)

Web page
Public communication of final result

Publications

Peer reviewed articles (5)

Barrier breakdown mechanism in nano-scale perpendicular magnetic tunnel junctions with ultrathin MgO barrier

Author(s): Hua Lv, Diana C. Leitao, Zhiwei Hou, Paulo P. Freitas, Susana Cardoso, Thomas Kämpfe, Johannes Müller, Juergen Langer, Jerzy Wrona
Published in: AIP Advances, Issue 8/5, 2018, Page(s) 055908, ISSN 2158-3226
Publisher: American Institute of Physics Inc.
DOI: 10.1063/1.5007656

The annealing effect on memory state stability and interlayer coupling in perpendicular magnetic tunnel junctions with ultrathin MgO barrier

Author(s): Hua Lv, João Fidalgo, Diana C. Leitão, Ana V. Silva, Thomas Kämpfe, Stefan Riedel, Juergen Langer, Jerzy Wrona, Berthold Ocker, Paulo P. Freitas, Susana Cardoso
Published in: Journal of Magnetism and Magnetic Materials, Issue 477, 2019, Page(s) 142-146, ISSN 0304-8853
Publisher: Elsevier BV
DOI: 10.1016/j.jmmm.2019.01.050

Pulse mode of operation – A new booster of TEG, improving power up to X2.7 – to better fit IoT requirements

Author(s): Maciej Haras, Michał Markiewicz, Stéphane Monfray, Thomas Skotnicki
Published in: Nano Energy, Issue In Press, 2019, Page(s) 104204, ISSN 2211-2855
Publisher: Elsevier BV
DOI: 10.1016/j.nanoen.2019.104204

Advanced FD-SOI and Beyond Low Temperature SmartCut™ Enables High Density 3-D SoC Applications

Author(s): W. Schwarzenbach, B.-Y. Nguyen, L. Ecarnot, S. Loubriat, M. Detard, E. Cela, C. Bertrand-Giuliani, G. Chabanne, C. Maddalon, N. Daval, C. Maleville
Published in: IEEE Journal of the Electron Devices Society, Issue 7, 2019, Page(s) 863-868, ISSN 2168-6734
Publisher: Institute of Electrical and Electronics Engineers Inc.
DOI: 10.1109/jeds.2019.2916460

Slicing FIFOs for On-Chip Memory Bandwidth Exhaustion

Author(s): Mattis Hasler, Robert Wittig, Emil Matus, Gerhard Fettweis
Published in: IEEE Transactions on Circuits and Systems I: Regular Papers, Issue Print ISSN: 1549-8328 Electronic ISSN: 1558-0806, 2019, Page(s) 1-10, ISSN 1549-8328
Publisher: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tcsi.2019.2926134

Conference proceedings (21)

Down to 15nm BOX: SOI extendability for planar fully depleted application beyond 22FD

Author(s): W. Schwarzenbach, F. Allibert, C. Le Royer, L. Grenouillet, C. Malaquin, C. Bertrand-Giuliani, F. Boedt, S. Loubriat, C. Michau, D. Parissi, B.-Y. Nguyen
Published in: 2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2016, Page(s) 1-2, ISBN 978-1-5090-4391-0
Publisher: IEEE
DOI: 10.1109/S3S.2016.7804377

Combined TDM and SDM Circuit Switching NoCs with Dedicated Connection Allocator

Author(s): Yong Chen, Emil Matus, Gerhard P. Fettweis
Published in: 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2017, Page(s) 104-109, ISBN 978-1-5090-6762-6
Publisher: IEEE
DOI: 10.1109/ISVLSI.2017.27

Combined packet and TDM circuit switching NoCs with novel connection configuration mechanism

Author(s): Yong Chen, Emil Matus, Gerhard P. Fettweis
Published in: 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 2017, Page(s) 1-4, ISBN 978-1-4673-6853-7
Publisher: IEEE
DOI: 10.1109/ISCAS.2017.8050829

A fixed point exponential function accelerator for a neuromorphic many-core system

Author(s): Johannes Partzsch, Sebastian Hoppner, Matthias Eberlein, Rene Schuffny, Christian Mayr, David R. Lester, Steve Furber
Published in: 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 2017, Page(s) 1-4, ISBN 978-1-4673-6853-7
Publisher: IEEE
DOI: 10.1109/ISCAS.2017.8050528

Dynamic voltage and frequency scaling for neuromorphic many-core systems

Author(s): Sebastian Hoppner, Yexin Yan, Bernhard Vogginger, Andreas Dixius, Johannes Partzsch, Felix Neumarker, Stephan Hartmann, Stefan Schiefer, Stefan Scholze, Georg Ellguth, Love Cederstroem, Matthias Eberlein, Christian Mayr, Steve Temple, Luis Plana, Jim Garside, Simon Davison, David R. Lester, Steve Furber
Published in: 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 2017, Page(s) 1-4, ISBN 978-1-4673-6853-7
Publisher: IEEE
DOI: 10.1109/ISCAS.2017.8050656

MESH: Explicit and flexible generation of analog arrays

Author(s): Benjamin Prautsch, Uwe Eichler, Torsten Reich, Jens Lienig
Published in: 2017 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2017, Page(s) 1-4, ISBN 978-1-5090-5052-9
Publisher: IEEE
DOI: 10.1109/SMACD.2017.7981572

Dynamic body bias for 22 nm FD-SOI CMOS Technology

Author(s): Nedelcu, Stefan; Voelker, Matthias; Klein, Leonhard; Schuhmann, Claudia; Schuhmann, Norbert; Hauer, Johann; Reich, Torsten; Rao, Sunil
Published in: 15. ITG/GMM-Symposium ANALOG 2016, Issue 15. ITG/GMM-Symposium ANALOG 2016, 2016, ISBN 978-3-8007-4265-3
Publisher: IEEE

Modeling and design considerations for negative capacitance field-effect transistors

Author(s): Michael Hoffmann, Milan Pesic, Stefan Slesazeck, Uwe Schroeder, Thomas Mikolajick, Thomas Mikolajick
Published in: 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Issue 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2017, Page(s) 1-4, ISBN 978-1-5090-5313-1
Publisher: IEEE
DOI: 10.1109/ulis.2017.7962577

Ultra-Low-Power SAR ADC In 22 Nm FD-SOI Technology Using Body-Biasing

Author(s): Jotschke, Marcel; Rao, Sunil Satish; Prautsch, Benjamin; Reich, Torsten
Published in: Semiconductor Engineering, 2019, ISBN 978-3-8007-4754-2
Publisher: Semiconductor Engineering

Energy-Efficient Hash Join Implementations in Hardware-Accelerated MPSoCs

Author(s): S Haas, G Fettweis
Published in: Eighth International Workshop on Accelerating Analytics and Data Management Systems Using Modern Processor and Storage Architectures, Issue Eighth International Workshop on Accelerating Analytics and Data Management Systems Using Modern Processor and Storage Architectures, 2017
Publisher: adms

A Hybrid Execution Approach to Improve the Performance of Dataflow Applications

Author(s): M Hasler, R Wittig, E Matus, G Fettweis
Published in: 16th International SoC Design Conference, 2019
Publisher: 16th International SoC Design Conference

Statistical Access Interval Prediction for Tightly Coupled Memory Systems

Author(s): Robert Wittig, Mattis Hasler, Emil Matus, Gerhard Fettweis
Published in: 2019 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS), Issue Annually, 2019, Page(s) 1-3, ISBN 978-1-7281-1749-2
Publisher: IEEE
DOI: 10.1109/coolchips.2019.8721304

A low-power BLE transceiver with support for phase-based ranging, featuring 5μs PLL locking time and 5.3ms ranging time, enabled by staircase-chirp PLL with sticky-lock channel-switching

Author(s): Elbert Bechthum, Johan Dijkhuis, Ming Ding, Yuming He, Johan van den Heuvel, Paul Mateman, Gert-Jan van Schaik, Kenichi Shibata*, Minyoung Song, Evgenii Tiurin, Stefano Traferro, Nick Winkel, Yao-Hong Li, Christian Bachmann
Published in: 2020 International Solid-State Circuits Conference, 2020
Publisher: 2020 International Solid-State Circuits Conference

Gewitter im Chip - Resistive Speicher für low-power Anwendungen (Chip-internal thunderstorm - resistive memories for low power applications)

Author(s): Drescher, Maximilian; Erben, Elke; Grass, Carsten; Trentzsch, Martin; Lazarevic, Florian; Leitsmann, Roman; Plaenitz, Philipp; Mchedlidze, Teimuraz; Seidel, Konrad; Liske, Romy; Bartha, Johann Wolfgang
Published in: MikroSystemTechnik Kongress 2017, Issue MikroSystemTechnik Kongress 2017, 2017, Page(s) pp.774-776, ISBN 978-3-8007-4491-6
Publisher: MikroSystemTechnik Kongress 2017

Beyond advanced FDSOI: Low Temp SmartCut for enabling High Density 3D SoC applications

Author(s): W. Schwarzenbach, B. -Y. Nguyen, L. Ecarnot, S. Loubriat, M. Detard, E. Cela, C. Bertrand-Giuliani, G. Chabanne, C. Maddalon, N. Daval, C. Girard, C. Maleville
Published in: 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Issue annually, 2018, Page(s) 1-2, ISBN 978-1-5386-7627-1
Publisher: IEEE
DOI: 10.1109/s3s.2018.8640192

Application Specific Instruction Processor for Dynamic Connection Allocation in TDM-NoCs

Author(s): S Nam, E Matus, G Fettweis
Published in: 32th IEEE International System-On-Chip Conference, 2019
Publisher: IEEE

Queue Based Memory Management Unit for Heterogeneous MPSoCs

Author(s): Robert Wittig, Mattis Hasler, Emil Matus, Gerhard Fettweis
Published in: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), Issue annually, 2019, Page(s) 1297-1300, ISBN 978-3-9819263-2-3
Publisher: IEEE
DOI: 10.23919/date.2019.8715129

Charakterisierung der Zuverlässigkeit in der High-k Metal Gate Technologie (Reliability characterization in High-k metal gate technology)

Author(s): Seidel, Konrad; Riedel, Stefan; Kalishettyhalli Ma, Mamathamba; Polakowski, Patrick; Müller, Johannes
Published in: MikroSystemTechnik Kongress 2017, Issue MikroSystemTechnik Kongress 2017, 2017, Page(s) pp.488-491, ISBN 978-3-8007-4491-6
Publisher: MikroSystemTechnik Kongress 2017

HW/SW-database-codesign for compressed bitmap index processing

Author(s): Sebastian Haas, Tomas Karnagel, Oliver Arnold, Erik Laux, Benjamin Schlegel, Gerhard Fettweis, Wolfgang Lehner
Published in: 2016 IEEE 27th International Conference on Application-specific Systems, Architectures and Processors (ASAP), Issue annually, 2016, Page(s) 50-57, ISBN 978-1-5090-1503-0
Publisher: IEEE
DOI: 10.1109/ASAP.2016.7760772

MESH: Explicit and Flexible Generation of Analog Arrays

Author(s): Benjamin Prautsch, Uwe Eichler, Torsten Reich, Jens Lienig
Published in: International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Issue annually, 2017
Publisher: IEEE

Body biasing for analog design: Practical experiences in 22 nm FD-SOI

Author(s): Sunil Satish Rao, Benjamin Prautsch, Ashish Shrivastava, Torsten Reich
Published in: 2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Issue annually, 2017, Page(s) 73-78, ISBN 978-1-5386-0472-4
Publisher: IEEE
DOI: 10.1109/DDECS.2017.7934580

Thesis and dissertations (1)

PVD and ALD process development of advanced oxide-based RRAM-stacks

Author(s): Kalishetthyhalli Mahadevaiah, Mamathamba
Published in: 2017
Publisher: Fraunhofer

Intellectual Property Rights

Patent (7)

Circuit for symbol timing synchronization

Application/Publication number: 14 153485
Date: 2014-01-31
Applicant(s): STICHTING IMEC NEDERLAND

PHASE TRACKING RECEIVER

Application/Publication number: 15 201303
Date: 2015-12-18
Applicant(s): STICHTING IMEC NEDERLAND

RECEIVER FOR FREQUENCY OFFSET CORRECTION

Application/Publication number: 16 169134
Date: 2016-05-11
Applicant(s): STICHTING IMEC NEDERLAND

DIGITAL PHASE LOCKED LOOP AND METHOD FOR OPERATING THE SAME

Application/Publication number: 16 186301
Date: 2016-08-30
Applicant(s): STICHTING IMEC NEDERLAND

MEMORY UNIT

Application/Publication number: 20 17051593
Date: 2017-06-02
Applicant(s): SURECORE LTD

METHOD FOR DISTANCE DETERMINATION

Application/Publication number: 17 209014
Date: 2017-12-20
Applicant(s): STICHTING IMEC NEDERLAND

METHOD TO REDUCE AGING OF A CACHE MEMORY

Application/Publication number: 18 175173
Date: 2018-05-30
Applicant(s): INTRINSIC ID BV