Periodic Reporting for period 3 - PRIME (Ultra-Low PoweR technologIes and MEmory architectures for IoT)
Periodo di rendicontazione: 2018-04-01 al 2019-09-30
The goal of the PRIME project is to establish an open Ultra Low Power (ULP) Technology Platform containing all necessary design and architecture blocks and components which could enable the European industry to increase and strengthen their competitive and leading eco-system and benefit from market opportunities created by the Internet of Things (IoT) revolution.
Over 3 years the project will develop and demonstrate the key building blocks of IoT ULP systems driven by the applications in the medical, agricultural, domestics and security domains. This will include development of high performance, energy efficient and cost effective technology platform, flexible design ecosystem (including IP and design flow), changes in architectural and power management to reduced energy consumption, security blocks based on PUF and finally the System of Chip and System in Package memory banks and processing implementations for IoT sensor node systems.
• Developped advanced as 22nm FDSOI low power technologies with logic, RF, first analog functionality.
• Embedded new memory components (STT RAM for 22-FDSOI and RRAM for 28 SLP)
• innovative design and system architecture solutions will be used to build macros and demonstrate functionality and power reduction advantage of the new IoT device components.
The PRIME project will realize several demonstrators of IoT system building blocks to show the proposed low power wireless solutions, functionality and performance of delivered design and technology blocks.
The consortium semiconductor ecosystem (IDMs, design houses, R&D, tools & wafer suppliers, foundries, system/product providers) covers complementarily all desired areas of expertise to achieve the project goals.
The project will enable an increase in Europe’s innovation capability in the area of ULP Technology, design and applications, creation of a competitive European eco-system and help to identify market leadership opportunities in security, mobility, healthcare and smart cost competitive manufacturing.
Over 3 years the project will develop and demonstrate the key building blocks of IoT ULP systems driven by the applications in the medical, agricultural, domestics and security domains. This will include development of high performance, energy efficient and cost effective technology platform, flexible design ecosystem (including IP and design flow), changes in architectural and power management to reduced energy consumption, security blocks based on PUF and finally the System of Chip and System in Package memory banks and processing implementations for IoT sensor node systems.
• Developped advanced as 22nm FDSOI low power technologies with logic, RF, first analog functionality.
• Embedded new memory components (STT RAM for 22-FDSOI and RRAM for 28 SLP)
• innovative design and system architecture solutions will be used to build macros and demonstrate functionality and power reduction advantage of the new IoT device components.
The PRIME project will realize several demonstrators of IoT system building blocks to show the proposed low power wireless solutions, functionality and performance of delivered design and technology blocks.
The consortium semiconductor ecosystem (IDMs, design houses, R&D, tools & wafer suppliers, foundries, system/product providers) covers complementarily all desired areas of expertise to achieve the project goals.
The project will enable an increase in Europe’s innovation capability in the area of ULP Technology, design and applications, creation of a competitive European eco-system and help to identify market leadership opportunities in security, mobility, healthcare and smart cost competitive manufacturing.
Consortium has completed the project successfully within the extended timeline. 100% of deliverables are delivered. More than 90% of the target specs of the deliverables were met. Scope of few deliverables were extended during the execution of the project and they were finished within the extended project timeline. Project was successfully completed with planned demonstrator demonstration during the final review meeting. Collaboration between different consortium partners crossed the border during the execution of the project in order to keep the predefine value of the deliverables and increase the value of the deliverables, in some cases. PRIME has demonstrated how an innovation IoT technology platform can be built based on the strong collaboration between partners. Following two new demonstrators were demonstrated.
Ranging IC from imec NL: Measuring distance between two nodes.
Predictive maintenance algorithm executed on chip and further transmission of the data over IP network using edge router using IMEC Mbit OxRAm array.
Consortium made several major progresses in technology development front. Following is the summary.
Evaluated several scenarios for a low power IoT “Swarm Node” and came with a conclusion:
For ULP design, using a NV-memory with an instruction cache is the best solution
For area constrained design, using only NV-memory is the best solution
A system study for the security of IoT nodes came with recommendations. With these findings WP2 gave input to WP4 and WP5 and a “Swarm node” SoC was taped out and demonstrators were built.
Qualification of thickness metrology tool and ultrathin BOX were delivered within the WP 3. Functional STT-MRAM with 22nm FDSOI as select transistor was developed. Demonstration of working OxRAM array and OxRAM performance qualification for IoT applications (additional system demo made) completed. CBRAM technology demonstrated its low power IoT application capability.
Low power memory system IP was developmed and accomplished major Power Reduction up to: 60% Dynamic, 70% Shutdown, 70% Standby. Technology down to 22nm was explored. Low-power ADC for second generation LiDAR system developed and in tape-out preparation (IDT). Cut power consumption into half compared to previous generation. Low power IP for secure key generation has been successfully integrated on the IMEC-NL swarm node SoC (Intrinsic-ID). Reduced power consumption by resource sharing for different functions (key generation and instruction cache). Application of Intelligent IP design flow in design and porting of a ULP SAR ADC in 350nm, GF22FDX and new: 180nm SOI; measurement of GF22FDX variant prove that major parts of design and porting of ultra-low – power IP can be automated.
The Ranging IC was taped out, Characterized, and measurement was carried out together with an FPGA for the ranging functionalities. The integrated IP from SureCore “Ultra-Low Voltage SRAM” and the IP from Intrinsic ID “the SRAM PUF technology” is working very successful on the PRIME “Swarm Node” SoC made by IMEC Nederland. HDR extension of the existing RPP (HDR RPP) works together with many available HDR sensors. Tapeout of TUD-Testchip and MPSoC in 22nm FDSOI was completed and design and manufacture of a low value custom BGA package was completed.
Finally, within the context of WP 6 we accomplished the following demonstrators. GF designed a 22FDSOI Test Chip to test functionality of digital devices, passive devices and RF-devices during process development. In addition, a Multiple Purpose memory test-chip was developed based on 28nm technology. IMEC-NL provided a demonstration board for the Swarm Node SoC. Synopsys demonstrated the power consumption benefits of the IP developed in the project in the application context of 9D sensor fusion. ST and CEZAMAT performed architecture, design and realization of two generations of PCB boards enabling fast prototyping. Intrinsic-ID developed a demonstrator that shows the properties of the designed security architecture for low-power IoT environments. Technolution developed a demonstrator for a realistic use case for NB-IoT.
Ranging IC from imec NL: Measuring distance between two nodes.
Predictive maintenance algorithm executed on chip and further transmission of the data over IP network using edge router using IMEC Mbit OxRAm array.
Consortium made several major progresses in technology development front. Following is the summary.
Evaluated several scenarios for a low power IoT “Swarm Node” and came with a conclusion:
For ULP design, using a NV-memory with an instruction cache is the best solution
For area constrained design, using only NV-memory is the best solution
A system study for the security of IoT nodes came with recommendations. With these findings WP2 gave input to WP4 and WP5 and a “Swarm node” SoC was taped out and demonstrators were built.
Qualification of thickness metrology tool and ultrathin BOX were delivered within the WP 3. Functional STT-MRAM with 22nm FDSOI as select transistor was developed. Demonstration of working OxRAM array and OxRAM performance qualification for IoT applications (additional system demo made) completed. CBRAM technology demonstrated its low power IoT application capability.
Low power memory system IP was developmed and accomplished major Power Reduction up to: 60% Dynamic, 70% Shutdown, 70% Standby. Technology down to 22nm was explored. Low-power ADC for second generation LiDAR system developed and in tape-out preparation (IDT). Cut power consumption into half compared to previous generation. Low power IP for secure key generation has been successfully integrated on the IMEC-NL swarm node SoC (Intrinsic-ID). Reduced power consumption by resource sharing for different functions (key generation and instruction cache). Application of Intelligent IP design flow in design and porting of a ULP SAR ADC in 350nm, GF22FDX and new: 180nm SOI; measurement of GF22FDX variant prove that major parts of design and porting of ultra-low – power IP can be automated.
The Ranging IC was taped out, Characterized, and measurement was carried out together with an FPGA for the ranging functionalities. The integrated IP from SureCore “Ultra-Low Voltage SRAM” and the IP from Intrinsic ID “the SRAM PUF technology” is working very successful on the PRIME “Swarm Node” SoC made by IMEC Nederland. HDR extension of the existing RPP (HDR RPP) works together with many available HDR sensors. Tapeout of TUD-Testchip and MPSoC in 22nm FDSOI was completed and design and manufacture of a low value custom BGA package was completed.
Finally, within the context of WP 6 we accomplished the following demonstrators. GF designed a 22FDSOI Test Chip to test functionality of digital devices, passive devices and RF-devices during process development. In addition, a Multiple Purpose memory test-chip was developed based on 28nm technology. IMEC-NL provided a demonstration board for the Swarm Node SoC. Synopsys demonstrated the power consumption benefits of the IP developed in the project in the application context of 9D sensor fusion. ST and CEZAMAT performed architecture, design and realization of two generations of PCB boards enabling fast prototyping. Intrinsic-ID developed a demonstrator that shows the properties of the designed security architecture for low-power IoT environments. Technolution developed a demonstrator for a realistic use case for NB-IoT.
This was an integral part of the review meeting. The presentation per partner was provided at the review meeting.
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