Energy Efficient Embedded Non-volatile Memory Logic based on Ferroelectric Hf(Zr)O2

Project Information

3eFERRO

Grant agreement ID: 780302

DOI

10.3030/780302

Project closed

EC signature date 31 October 2017

Start date 1 January 2018

End date 30 June 2021

Funded under

• INDUSTRIAL LEADERSHIP - Leadership in enabling and industrial technologies - Information and Communication Technologies (ICT)

Total cost

€ 3 989 571,41

EU contribution

€ 3 989 570,20

Coordinated by

COMMISSARIAT A L ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
France

Periodic Reporting for period 3 - 3eFERRO (Energy Efficient Embedded Non-volatile Memory Logic based on Ferroelectric Hf(Zr)O2)

Reporting period: 2020-07-01 to 2021-06-30

Summary of the context and overall objectives of the project

The Internet of things (IoT) technology is deployed in 5 main areas: Smart Environment for ageing well, Smart Farming, Wearable, Smart Cities, and Smart Mobility. Development and optimization of the technology has potentially important consequences in terms of economic competitiveness, employment, energy conservation, living conditions and lifestyle.
However, the rapid growth of the IoT requires intelligent, fast and low power data handling and storage well beyond current capacities.
Data transfer between the central processor unit and adjacent embedded non-volatile memory (eNVM) is the most simple approach but more complex and efficient approaches are required to optimize handling and power consumption. This would allow replacing Flash memories in microcontrollers by better embedded elements in logic circuits for local storage and non-volatile circuits. New, more robust and faster eNVMs with low power consumption and higher endurance would enable the implementation of more flexible logic and memory architectures.

Work performed from the beginning of the project to the end of the period covered by the report and main results achieved so far

In the first 9 months of the project the exchange protocols, materials growth and first advanced characterization experiments were performed. Ferroelectric HfO2 and HfZrO2 can be produced by a wide variety of techniques in four partner laboratories. In parallel, the test design for producing and characterizing an array of ferroelectric memory devices has been validated, allowing production of the first demonstrator to be planned.
During the M10-M18 reporting period, materials growth and optimization has expanded, including ALD, PLD, PVD and MBD production of ferroelectric HfZrO for both FeRAMs and using Ge substrates for FeFETs. Negative capacitance was demonstrated using a double layer (dielectric/ferroelectric). Advanced characterization now includes hard and soft X-ray photoelectron spectroscopy with operando experiments in the pipeline. Excellent HfZrO on Ge has been achieved with record high remanent polarization that sets the basis for novel FeFETs, expected to overcome the shortcomings of Si FeFETs.
The specifications of FE capacitances, sense amplifier design and peripheral circuits design have been completed. We have successfully integrated sub µm² ferroelectric (FE) capacitors in the BEOL of 130 nm node CMOS 200 mm wafers and carried out a first electrical validation of 1T-1C functionality.
The design of a system-level benchmarking platform for Normally-off (N-off) computing architectures was initiated. As a first Logic-in-Memory (LiM) application, design of a real time image filter circuit using a non-volatile kernel was started.
For the reporting period M19-M30, it was decided to integrate the optimized La doped HZO on MAD200v3 wafers, for the final 16kbit 1T-1C FeRAM array demonstrator.
Si:HfO2 films have shown much better device-to-device and die-to-die variability than HZO films. Retention measurements showed stable performance at 85°C and it was decided to integrate them onto an additional final demonstrator.
Gate stacks with different ferroelectric/dielectric bilayers have provided insight into the negative capacitance effect and input for the fabrication of the proof-of-concept NC-FeFET.
Two FeFET structures are addressed: p-Ge/HZO/TiN and n-Ge/HZO/TiN stacks for exploring the potential benefits of Ge channel and Si-based NC structures.
Exploratory FeRAM-based structures have been designed for inclusion in the MAD200v3 demonstrator to evaluate suitability for N-Off computing and coarse-grain LiM. Three test structures will be included: 2TnC, ternary content addressable memory and pseudo-FeFET. The image filter design, implementing HZO based FeFET logic, has been completed
Finally, the system-level benchmarking platform, designed to assess performance impact of both device-level and architectural design choices, is now operational.
For the final reporting period (M31-M42)
The 16kbit 1T-1C FeRAM demonstrators using HZO and Si-doped HfO2 have been produced and characterized.
Innovative LiM structures, including pseudo FeFETs, TCAMs and 2T-1C devices have been produced.
HZO/Ge interfaces have been characterized in terms of chemistry and also imprint behavior.
The MPW using 28 nm node has been produced by GF and the image filter tested.
Interface engineering using Ti layers and correlations between chemistry and ferroelectric properties have been studied.
The charge injection into HZO films during writing has been addressed.
Retention for temperatures between 85 and 125°C has been quantified for HZO capacitors.
A YouTube video for a general public presentation of the project work has been produced.

Progress beyond the state of the art and expected potential impact (including the socio-economic impact and the wider societal implications of the project so far)

Ferroelectric memories (FRAMs) have the best endurance among all NVMs with a very low energy per bit of information. The recent discovery of ferroelectricity in HfO2 has opened the way to high-density integration of these memories in current semiconductor technology. 3εFERRO therefore aims to develop a competitive and versatile ferroelectric HfO2-based embedded memory devices. In 2019, for the first time, functional HfO2-based MFM NVM arrays have been integrated with CMOS using appropriate 200 mm pilot line.
Secondly, the project will develop new electronic circuit designs to optimize speed and power consumption for mobile devices and IoT applications.
Thirdly, proof of principle of negative capacitance devices is targeted.

Project logo

SEM cross-section showing transistor level and BEOL HZO FRAMs