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Modeling critical reliability issues in VLSI technologies beyond 2020

Periodic Reporting for period 1 - MoCRIV (Modeling critical reliability issues in VLSI technologies beyond 2020)

Reporting period: 2018-08-22 to 2020-08-21

Although transistor scaling has been actively exploited for more than 50 years, MOSFET technology has still to go for many years. However, any further developments and progress can only be achieved by acquiring and retaining a thorough understanding of the microscopic physics underlying the behavior of novel devices/materials. Unlike the more tangible product parameters, such as performance or power consumption, reliability specifications are often neither disclosed nor considered by the typical end-user. However, reliability is the essential metric required for the introduction of each new VLSI node. Therefore, the primary goal of this project has been to develop and validate a physics-based modeling framework which captures the main reliability phenomena to obtain realistic reliability projections for future nodes.

This framework should accurately model three main reliability issues in modern transistors – namely bias temperature instability (BTI), hot-carrier degradation (HCD), and self-heating (SH) – in devices with different channel materials, various geometries, and stressed using a broad range of conditions.
Within 24 months of the project, MoCRIV has achieved most of its research goals. The training and public outreach activities have been achieved as well. In the initial research plan, the objective 4 was devoted to reliability concerns in InGaAs transistors. However, these devices were removed from the IMEC roadmap because of large sample-to-sample variability found in them, therefore objective 4 has been revised to focus on HCD induced variability in Si FETs. The following project objectives have been addressed:
1. A starting point of the project was coupling BTI and HCD models for planar transistors, followed by validation of the unified model over a wide range of stress conditions.
2. The unified model for BTI and HCD was then extended to 3D transistors. In these structures, SH is inevitable and its impact on device degradation was captured by the extended model.
3. Further expansion of the modeling framework was focused on inclusion of HCD in SiGe/Ge devices. For this, defects responsible for HCD were identified. This goal was achieved with ab initio calculations.
4. Based on the deterministic version of our HCD model, a stochastic approach to HCD modeling was developed and applied to HCD in Si devices.
The research within the WP1 was devoted to coupling BTI and HCD models for planar Si FETs. First, we extended the BTI model to model trapping of non-equilibrium hot carriers. To achieve this goal, we modeled trapping rates using non-equilibrium carrier energy distribution functions obtained as a solution of the Boltzmann transport equation. Then, the model for non-equilibrium BTI was coupled to the HCD model and applied to HCD stress → BTI stress → relaxation and BTI stress → HCD stress → relaxation sequences. An important result is that for the latter sequence secondary carriers generated by impact ionization can stimulate recovery of BTI. Moreover, we showed that secondary carriers result in a portion of damage spread over the entire device. Finally, the BTI-HCD model was validated over a wide range of stress conditions and demonstrated good accuracy.

In WP2, the HCD-BTI model was extended to capture HCD and BTI in 3D transistor structures such as FinFETs and NWFETs. Our HCD model (Fig. 1) covers three main aspects: (1) carrier transport, (2) defect generation mechanisms, and (3) simulations of the degraded devices. In FinFETs/NWFETs, SH plays a crucial role and hence we extended the HCD model by coupling the Boltzmann transport equation solver to a lattice heat flow equation solver. We showed that in n-channel 3D FETs, SH depopulates high energy fraction of the carrier ensemble. This impact and the increased contribution to the thermal damage compensate each other and therefore the impact of SH on HCD is weak. This result is consistent with experimental observations. Vice versa, in p-channel FETs, these factors enhance HCD and the model can capture this behavior. Finally, our framework was shown to accurately model HCD-SH over a wide range of stress conditions in various devices. Coupling HCD and BTI models was performed within the analytical simulation framework which is suitable for compact modeling of device degradation at the circuit level.

WP3 was primarily devoted to modeling of HCD in SiGe/Ge devices. We identified that HCD in these FETs is dominated by dissociation of Ge-O bonds (precursors) followed by formation of O vacancies (traps), on top of rupture of Si-H bonds typical for HCD in Si devices. Conducted first principles calculations allowed us to obtain the pathway for the Ge-O bond dissociation reaction, as well as vibrational properties of the bond (needed for SH modeling). The model for HCD-SH in SiGe/Ge FETs accurately covers degradation characteristics for different stress conditions and can explain superior robustness of Ge pNWFETs compared to their Si counterparts.
The modified WP4 has been refocused on a stochastic description of HCD in Si devices. We analyzed impacts of random dopants (RDs) and random traps (RTs) on HCD in nFinFETs. For that, we generated 200 different instantiations of the transistor where each of them has a unique configuration of RDs, solved the Boltzmann transport equation, and obtained the continuous interface state density Nit, which was further randomized to generated 200 instantiations with unique configurations of RTs (in total 40,000 different configurations of RDs and RTs). Then we modeled changes of the linear drain current with time and extracted devices lifetimes. We showed that degradation characteristics have broad distributions and the deterministic HCD model tends to overestimate HCD. Further, distributions of device lifetimes are bi-modal and therefore reflect impacts of RDs and RTs. We also identified correlation between time-0 and HCD induced variabilities.
Finally, within the WP5 we monitored the progress and arising issues, discussed potential risks and corrections to the initial research plan
There are several main outcomes beyond the state of the art:
Physics-based description of the impact of SH on HCD enabled in 3D structures and explanation why in n-cannel FETs this impact is weak while in p-channel transistors SH substantially enhances HCD.
Identification of defects/precursors responsible for hot-carrier degradation in SiGe/Ge devices and explanation of superior HC robustness of Ge pNWFETs compared to their Si counterparts.
Stochastic description of HCD in scaled devices based on thorough carrier transport treatment
A schematic representation of our framework for consistent HCD-SH modeling